usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity
757 commits 1 branch 0 tags 3.8 MiB
Commit graph

49 commits

Author SHA1 Message Date
whitequark ffd10e3042 back.rtlil: fix lowering of Part() on LHS to account for stride. 2019-10-26 01:52:34 +00:00
whitequark 706bfaf5e1 hdl.ast: deprecate Signal.{range,enum}. 
Although constructor methods can improve clarity, there are many
contexts in which it is useful to use range() as a shape: notably
Layout, but also Const and AnyConst/AnyValue. Instead of duplicating
these constructor methods everywhere (which is not even easily
possible for Layout), use casting to Shape, introduced in 6aabdc0a.

Fixes #225.
 2019-10-11 13:07:42 +00:00
whitequark 7dfd7fb12a examples: update blinky, add some explanatory text about domains. 2019-10-09 23:19:28 +00:00
whitequark 8deb13cea3 lib.cdc: MultiReg→FFSynchronizer. 
Fixes #229.
 2019-09-23 14:18:45 +00:00
whitequark eb04a2509e hdl.mem,lib,examples: use Signal.range(). 2019-09-08 12:19:13 +00:00
whitequark 5e9587bbbd Remove nmigen.lib from prelude. 
Currently it's just MultiReg, and there's no particularly good reason
to privilege this specific CDC primitive so much.
 2019-09-06 06:53:06 +00:00
Reto Kramer b0ef53e095 examples/basic/uart: document divisor parameter. 2019-08-22 19:28:40 +00:00
whitequark fa0fa056ba hdl.xfrm: CEInserter→EnableInserter. 
Fixes #166.
 2019-08-12 13:39:26 +00:00
whitequark 5c63177fc2 test: generate examples to verilog as part of unit tests. 
This is to make sure 806a62c2 doesn't happen again.
 2019-07-08 10:12:26 +00:00
whitequark c14d074fcc examples/basic/ctr_ce: fix outdated syntax. 2019-07-08 10:12:26 +00:00
whitequark 2b92f12016 examples: add concise UART example. 
This example uses shift registers and counters instead of an explicit
FSM, which makes it very compact in terms of generated logic, and
more concise too.
 2019-06-27 04:51:45 +00:00
whitequark 1b54eb80da vendor.board: split off into nmigen-boards package. 
The iCE40 programmers are also moved, since they're board-specific.
(It looks like iceprog isn't, but it only works with Lattice
evaluation kits.)

Fixes #80.
 2019-06-04 09:52:33 +00:00
whitequark 3d04122d55 examples: reorganize into examples/basic and examples/board. 2019-06-03 16:17:37 +00:00
whitequark 0fa45b5e14 vendor.board: extract package. 2019-06-03 16:14:59 +00:00
whitequark f417725b10 build.res: if not specified, request resource #0. 
This markedly differs from oMigen system, which would request
consecutive resources. The difference is deliberate; most resources
are singular, so it does not matter for them, and for resources where
it does matter, which pins are requested should not depend on order
of execution of `platform.request`.
 2019-06-03 02:54:17 +00:00
whitequark ba0fcddb2c vendor.ice40_hx1k_blink_evn: implement. 2019-06-01 16:48:07 +00:00
whitequark aed2062101 Remove examples/tbuf.py. 
This example predates the plans for nmigen.build, and indeed
get_tristate and TSTriple no longer exist.
 2019-04-21 08:53:37 +00:00
whitequark 44711b7d08 hdl.ir: detect elaboratables that are created but not used. 
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.

Fixes #3.
 2019-04-21 08:52:57 +00:00
Alain Péteut d69a4e29a8 examples.por: fix typo 2019-03-12 02:14:21 +00:00
whitequark 7acea8f3ce examples: update for newer API. 2019-01-26 16:25:05 +00:00
whitequark 4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark 6f66885c09 lib.io: lower to platform-independent tristate buffer. 2019-01-14 16:50:04 +00:00
whitequark 011bf2258e hdl: make ClockSignal and ResetSignal usable on LHS. 
Fixes #8.
 2019-01-14 15:38:16 +00:00
whitequark 92a96e1644 hdl.rec: add basic record support. 2018-12-28 13:22:10 +00:00
whitequark 470d66934f hdl.dsl: add support for fsm.ongoing(). 2018-12-27 16:19:01 +00:00
whitequark 597d778cf6 examples: add an FSM usage example (UART receiver). 2018-12-26 10:10:27 +00:00
whitequark cf79738744 cli: new module, for basic design generaton/simulation. 2018-12-23 00:06:58 +00:00
whitequark a061bfaa6c hdl.mem: tie rdport.en high for asynchronous or transparent ports. 2018-12-21 04:22:16 +00:00
whitequark 2b4a8510ca back.rtlil: implement memories. 2018-12-21 01:55:59 +00:00
whitequark f7fec804ec ir: allow non-Signals in Instance ports. 2018-12-20 23:40:40 +00:00
whitequark c7f9386eab fhdl.ir: add black-box fragments, fragment parameters, and Instance. 2018-12-17 22:55:39 +00:00
whitequark 850674637a back.rtlil: implement Array. 2018-12-17 01:15:23 +00:00
whitequark 1adf58f561 examples: rename clkdiv/ctrl to ctr/ctr_ce. 2018-12-15 20:42:52 +00:00
whitequark b5a1efa0c8 Move star imports to make from nmigen import * usable. 2018-12-15 14:20:10 +00:00
whitequark 9307a31678 back.pysim: Simulator({gtkw_signals→traces}=). 2018-12-14 15:23:22 +00:00
whitequark dd00b5e2d6 back.pysim: more general clean-up. 2018-12-14 12:46:04 +00:00
whitequark a10791e160 back.pysim: if requested, write a gtkw file with a useful preset. 2018-12-14 08:04:29 +00:00
whitequark 3bb7a87e0f back.pysim: implement "sync processes", like migen.sim generators. 2018-12-14 05:13:58 +00:00
whitequark d791b77cc8 back.pysim: allow suspending processes until a tick in a domain. 2018-12-14 04:33:06 +00:00
whitequark 6a4004ef8d back.pysim: fix handling of process termination. 2018-12-13 18:17:58 +00:00
whitequark fb27c2520b back.pysim: new simulator backend (WIP). 2018-12-13 18:02:46 +00:00
whitequark bb04c9e0da fhdl, back: trace and emit source locations of values. 2018-12-13 11:44:06 +00:00
whitequark 72257b6935 fhdl.ir: implement clock domain propagation. 2018-12-13 11:01:03 +00:00
whitequark 932f1912a2 fhdl.dsl: use less error-prone Switch/Case two-level syntax. 2018-12-13 07:11:06 +00:00
whitequark ad9b45adcd fhdl.ir: fix port threading code. 2018-12-12 13:00:50 +00:00
whitequark 0fac1f8d0f fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix. 2018-12-12 12:38:24 +00:00
whitequark bc60631d68 genlib.cdc.MultiReg: pull in from Migen. 2018-12-12 10:12:35 +00:00
whitequark 851ed06769 ClockDomain.{rst→reset}, for consistency with ResetInserter. 
nmigen.compat.ClockDomain would alias this, for Migen compatibility.
 2018-12-12 09:49:02 +00:00
whitequark 4d3258013d Initial commit. 2018-12-12 03:18:44 +00:00