$verilog_initial_trigger was introduced to work around Verilog
simulation semantics issues with `always @*` statements that only
have constants on RHS and in conditions. Unfortunately, it breaks
Verilator. Since the combination of proc_prune and proc_clean passes
eliminates all such statements, it can be simply removed when both
of these passes are available, currently on Yosys master. After
Yosys 0.10 is released, we can get rid of $verilog_initial_trigger
entirely.
Also, replace `bits, sign = x.shape()` with more idiomatic
`width, signed = x.shape()`.
This unifies all properties corresponding to `len(x)` to `x.width`.
(Not all values have a `width` property.)
Fixes#210.
Because Fragment.prepare is not (currently) idempotent, it is useful
to be able to avoid calling it when converting. Even if it is made
idempotent, it can be slow on large designs, so it is advantageous
regardless of that.
Using 'x is legal RTLIL, in theory, but in practice it crashes Yosys
and when it doesn't, it causes Yosys to produce invalid Verilog.
Using a dummy wire is always safe and is not a major readability
issue as this is a rare corner case.
(It is not trivial to shorten the RHS in this case, because during
expansion of an ArrayProxy, match_shape() could be called in
a context far from the RHS handling logic.)
This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.
Also fixes incorrect source location on value.part().
This gives particularly pathological results on IO buffers, like:
connect \D_OUT_0 \user_led_0_user_led_0__o
Since subfragment signals are name-prefixed because this works well
for signals propagated upwards across hierarchy, this is never
desirable for instances.
This effectively reverts and reimplements half of commit 82903e49.
I was confused and did not realize that RTLIL does, in fact, have
attributes on switches.
After this commit, processes no longer have any source locations.
This is semantically fine, as the processes we emit are purely
artificial (because of LHS grouping), but I have not checked how
downstream tooling handles this.
According to RTLIL semantics (that was undocumented before today),
the only purpose of `sync always` is to enable inference of latches,
because there is no other way to express them in terms of RTLIL
processes without ending up with a combinatorial loop. But, nMigen
specifically avoids latches, so this is not necessary.
This change results in major improvements in Verilog readability.
See also #98.
This means that instead of:
with m.Case(0b00):
<body>
with m.Case(0b01):
<body>
it is legal to write:
with m.Case(0b00, 0b01):
<body>
with no change in semantics, and slightly nicer RTLIL or Verilog
output.
Fixes#103.
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.
While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
Otherwise the following code fails to compile:
index = Signal(1)
array = Array(range(2))
with m.If(0 == array[index]):
m.d.sync += index.eq(0)
Fixes#51.
