whitequark
|
1f10bd96b9
|
Determine Migen's API surface and document compatibility summary.
This also reorganizes README to more clearly describe what nMigen is,
since it was getting quite outdated.
|
2018-12-15 11:52:30 +00:00 |
|
whitequark
|
db4600d52b
|
fhdl.ast, back.pysim: implement shifts.
|
2018-12-15 09:58:30 +00:00 |
|
whitequark
|
46f5addf05
|
fhdl.ast: refactor Operator.shape(). NFC.
|
2018-12-15 09:46:20 +00:00 |
|
whitequark
|
3a8685c352
|
Consistently use '{!r}' in and only in TypeError messages.
|
2018-12-15 09:31:58 +00:00 |
|
whitequark
|
f5e8c9033d
|
fhdl.ir: fix incorrect uses of positive to say non-negative.
Also test Part and Slice properly.
|
2018-12-15 09:26:23 +00:00 |
|
whitequark
|
ecea721f43
|
compat.fhdl.module: allow adding native submodules to compat modules.
|
2018-12-14 23:56:50 +00:00 |
|
whitequark
|
1c7b43ea49
|
Fix deprecations in Python 3.7.
|
2018-12-14 23:56:50 +00:00 |
|
whitequark
|
c4ba5a3915
|
fhdl.ast: clean up stub error messages. NFC.
|
2018-12-14 23:07:16 +00:00 |
|
whitequark
|
2001359b66
|
fhdl.ir: automatically flatten hierarchy to resolve driver conflicts.
Fixes #5.
|
2018-12-14 22:48:17 +00:00 |
|
whitequark
|
579feaba4e
|
fhdl.ir: Fragment.{drive→add_driver}
|
2018-12-14 20:58:29 +00:00 |
|
whitequark
|
50ba443f92
|
fhdl.ast: fix Switch with constant test.
|
2018-12-14 16:09:51 +00:00 |
|
whitequark
|
474d46ced8
|
back.pysim: implement most operators and add tests.
|
2018-12-14 14:21:22 +00:00 |
|
whitequark
|
3ad79ec690
|
back.pysim: allow processes to evaluate expressions.
|
2018-12-14 13:32:30 +00:00 |
|
whitequark
|
151d079f01
|
fhdl.ir: oops, we defined DomainError twice.
|
2018-12-14 12:59:54 +00:00 |
|
whitequark
|
7d91dd56c8
|
fhdl.xfrm: implement DomainLowerer.
|
2018-12-14 10:56:53 +00:00 |
|
whitequark
|
b34c1a9ad0
|
back.pysim: undriven comb signals should return to reset value.
|
2018-12-14 09:12:38 +00:00 |
|
whitequark
|
b58715c5dc
|
ast, back.pysim: allow specifying user-defined decoders for signals.
|
2018-12-14 09:02:29 +00:00 |
|
whitequark
|
d791b77cc8
|
back.pysim: allow suspending processes until a tick in a domain.
|
2018-12-14 04:33:06 +00:00 |
|
whitequark
|
3e59d857e1
|
back.pysim: use bare ints for signal values (-5% runtime).
|
2018-12-14 03:05:57 +00:00 |
|
whitequark
|
fb27c2520b
|
back.pysim: new simulator backend (WIP).
|
2018-12-13 18:02:46 +00:00 |
|
whitequark
|
71f1f717c4
|
fhdl.cd: rename ClockDomain signals together with domain.
|
2018-12-13 15:24:55 +00:00 |
|
whitequark
|
07c818e077
|
fhdl.ir: move Fragment prepare logic from back.rtlil.
|
2018-12-13 14:34:07 +00:00 |
|
whitequark
|
90f1503c91
|
fhdl.ir: record port direction explicitly.
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
|
2018-12-13 13:12:31 +00:00 |
|
whitequark
|
6251c95d4e
|
compat.genlib.fsm: import/wrap Migen code.
|
2018-12-13 12:41:19 +00:00 |
|
whitequark
|
9661e897e6
|
fhdl.ir: a subfragment's input that we don't drive is also our input.
|
2018-12-13 11:50:56 +00:00 |
|
whitequark
|
bb04c9e0da
|
fhdl, back: trace and emit source locations of values.
|
2018-12-13 11:44:06 +00:00 |
|
whitequark
|
b150f1915d
|
fhdl.ir: don't crash propagataing ports in empty fragments.
|
2018-12-13 11:25:49 +00:00 |
|
whitequark
|
72257b6935
|
fhdl.ir: implement clock domain propagation.
|
2018-12-13 11:01:03 +00:00 |
|
whitequark
|
fde2471963
|
fhdl.ir: remove iter_domains().
|
2018-12-13 10:18:57 +00:00 |
|
whitequark
|
f4340c19bb
|
fhdl: cd_name→domain.
|
2018-12-13 10:15:01 +00:00 |
|
whitequark
|
c5087edfa5
|
fhdl.cd: add tests.
|
2018-12-13 09:19:16 +00:00 |
|
whitequark
|
9bee90f1bd
|
fhdl.xfrm: implement DomainRenamer.
|
2018-12-13 08:57:14 +00:00 |
|
whitequark
|
19aa404628
|
fhdl.xfrm: add tests for ResetInserter, CEInserter.
|
2018-12-13 08:39:02 +00:00 |
|
whitequark
|
b1a89ef5fd
|
fhdl.ir: add tests for port propagation.
|
2018-12-13 08:09:39 +00:00 |
|
whitequark
|
d2e2d00e45
|
fhdl.cd: rename ClockDomain.{reset→rst}.
|
2018-12-13 07:27:27 +00:00 |
|
whitequark
|
e0a81edf4d
|
fhdl.dsl: add tests for submodules.
|
2018-12-13 07:24:28 +00:00 |
|
whitequark
|
932f1912a2
|
fhdl.dsl: use less error-prone Switch/Case two-level syntax.
|
2018-12-13 07:11:06 +00:00 |
|
whitequark
|
f70ae3bac5
|
fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
|
2018-12-13 06:06:51 +00:00 |
|
whitequark
|
5b8708017e
|
fhdl.ast: fix Switch._?hs_signals() for switch without statements.
|
2018-12-13 05:00:44 +00:00 |
|
whitequark
|
4df5c5de65
|
fhdl.ir: explain how port enumeration works.
|
2018-12-13 03:31:13 +00:00 |
|
whitequark
|
bfd0011aee
|
fhdl.ir: make sure clocks and resets of used CDs appear as inputs.
|
2018-12-13 02:43:22 +00:00 |
|
whitequark
|
22c76e5f90
|
compat.fhdl.module: implement finalization.
|
2018-12-13 02:36:15 +00:00 |
|
whitequark
|
f0f4c0ce61
|
fhdl.ast: bits_sign→shape.
|
2018-12-13 02:06:58 +00:00 |
|
whitequark
|
dc486ad8b9
|
fhdl.ast: add tests for most logic.
|
2018-12-13 02:06:55 +00:00 |
|
whitequark
|
b4dab74b2e
|
compat.fhdl.{module,structure}: import/wrap Migen code (WIP).
|
2018-12-12 15:47:34 +00:00 |
|
whitequark
|
1d4d00aac6
|
fhdl.ast.Signal: implement .like().
|
2018-12-12 14:43:19 +00:00 |
|
whitequark
|
ad9b45adcd
|
fhdl.ir: fix port threading code.
|
2018-12-12 13:00:50 +00:00 |
|
whitequark
|
0fac1f8d0f
|
fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
|
2018-12-12 12:38:24 +00:00 |
|
whitequark
|
00f0b950f6
|
fhdl.ast.Signal: fix typo.
|
2018-12-12 12:37:30 +00:00 |
|
whitequark
|
aab01d9e59
|
fhdl.ast.Signal: implement attrs field.
|
2018-12-12 11:30:40 +00:00 |
|