whitequark
a40e2cac4b
back.pysim: fix an issue with too few funclet slots.
2018-12-21 10:25:28 +00:00
whitequark
a061bfaa6c
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
2018-12-21 04:22:16 +00:00
whitequark
8d58cbf230
back.rtlil: more consistent prefixing for subfragment port wires.
2018-12-21 04:21:11 +00:00
whitequark
2b4a8510ca
back.rtlil: implement memories.
2018-12-21 01:55:59 +00:00
whitequark
6672ab2e3f
back.rtlil: explicitly pad constants with zeroes.
...
I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.
2018-12-21 01:51:18 +00:00
whitequark
221f108fbe
back.rtlil: fix translation of Cat.
2018-12-21 01:48:02 +00:00
whitequark
f7fec804ec
ir: allow non-Signals in Instance ports.
2018-12-20 23:40:40 +00:00
whitequark
dbbcc49a71
hdl.ast: Cat.{operands→parts}
2018-12-18 19:15:50 +00:00
whitequark
4199674edd
back.pysim: implement *.
2018-12-18 18:02:21 +00:00
whitequark
07e9cfa939
test.sim: add tests for sync functionality and errors.
2018-12-18 17:53:50 +00:00
whitequark
7fa82a70be
back.pysim: eliminate most dictionary lookups.
...
This makes the Glasgow testsuite about 30% faster.
2018-12-18 16:36:54 +00:00
whitequark
c5f169988b
back.pysim: use arrays instead of dicts for signal values.
...
This makes the Glasgow testsuite about 40% faster.
2018-12-18 05:20:20 +00:00
whitequark
39605ef551
back.pysim: naming. NFC.
2018-12-18 04:46:36 +00:00
whitequark
65702719e8
back.pysim: fix an off-by-1 in add_sync_process().
2018-12-18 04:43:04 +00:00
whitequark
34b81d0b87
back.pysim: trigger processes waiting on Tick() exactly at clock edge.
2018-12-18 04:37:39 +00:00
whitequark
d6e98fd934
back.pysim: continue running simulator processes until they suspend.
2018-12-18 03:05:16 +00:00
whitequark
c7f9386eab
fhdl.ir: add black-box fragments, fragment parameters, and Instance.
2018-12-17 22:55:39 +00:00
whitequark
8d1639a5a8
hdl, back: add and use SignalSet/SignalDict.
2018-12-17 17:21:29 +00:00
whitequark
f1e390cbc9
back.rtlil: update for Yosys master.
2018-12-17 15:50:43 +00:00
whitequark
850674637a
back.rtlil: implement Array.
2018-12-17 01:15:23 +00:00
whitequark
87cd045ac3
back.rtlil: implement Part.
2018-12-17 01:05:08 +00:00
whitequark
f968678937
back.rtlil: handle reset_less domains.
2018-12-16 23:52:47 +00:00
whitequark
91b7561a00
back.rtlil: extract _StatementCompiler. NFC.
2018-12-16 22:26:58 +00:00
whitequark
b9a0af8bde
back.rtlil: simplify. NFC.
2018-12-16 21:00:00 +00:00
whitequark
635094350f
back.rtlil: properly escape strings in attributes.
2018-12-16 20:27:36 +00:00
whitequark
33f32a25f5
back.rtlil: prepare for Yosys sigspec slicing improvements.
...
See YosysHQ/yosys#741 .
2018-12-16 18:03:14 +00:00
whitequark
9bce35098f
back.rtlil: avoid illegal slices.
...
Not sure what to do with {} [] on LHS yet--fix Yosys?
2018-12-16 17:41:11 +00:00
whitequark
e86104d3a6
back.rtlil: use slicing to match shape when reducing width.
2018-12-16 16:20:45 +00:00
whitequark
2833b36c73
back.rtlil: don't emit a slice if all bits are used.
2018-12-16 16:05:38 +00:00
whitequark
9794e732e2
back.rtlil: reorganize value compiler into LHS/RHS.
...
This also implements Cat on LHS.
2018-12-16 13:33:34 +00:00
whitequark
ed39748889
back.rtlil: fix naming. NFC.
2018-12-16 11:26:31 +00:00
whitequark
2be76fda3c
hdl.xfrm: separate AST traversal from AST identity mapping.
...
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
2018-12-16 11:25:52 +00:00
whitequark
d4e8d3e95a
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
2018-12-16 10:31:42 +00:00
whitequark
bdb8db2826
back.pysim: add (stub) LHSValueCompiler.
2018-12-15 21:01:38 +00:00
whitequark
20a04bca88
back.pysim: implement Part.
2018-12-15 20:58:06 +00:00
whitequark
54fb999c99
back.pysim: implement ArrayProxy.
2018-12-15 19:37:36 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
whitequark
db4600d52b
fhdl.ast, back.pysim: implement shifts.
2018-12-15 09:58:30 +00:00
whitequark
3a8685c352
Consistently use '{!r}' in and only in TypeError messages.
2018-12-15 09:31:58 +00:00
whitequark
7108111ad0
back.pysim: preserve process locations through add_sync_process().
2018-12-14 23:27:36 +00:00
whitequark
0015713bfb
back.pysim: count delta cycles separately to avoid clock drift.
2018-12-14 20:52:41 +00:00
whitequark
a6a8703a0e
back.pysim: simplify.
2018-12-14 20:45:45 +00:00
whitequark
7e3cf26cf8
back.pysim: revert 70ebc6f2.
2018-12-14 19:46:08 +00:00
whitequark
71304c9fe7
back.pysim: fix implicit boolean conversion.
2018-12-14 19:08:06 +00:00
whitequark
fe5fb34fae
back.pysim: squash one level of hierarchy.
...
There's really no point in the "top" node.
2018-12-14 18:53:21 +00:00
whitequark
70ebc6f2c1
back.pysim: implement blocking assignment semantics correctly.
2018-12-14 18:47:12 +00:00
whitequark
120d817123
back.pysim: undriven sync signals should return to previous value.
2018-12-14 17:25:48 +00:00
whitequark
4f5b4a9bf4
back.pysim: in simulator sync processes, start by waiting for a tick.
...
This matches Migen behavior and also makes more sense.
2018-12-14 17:05:11 +00:00
whitequark
e230383aac
back.pysim: make initial phase configurable.
2018-12-14 16:46:16 +00:00
whitequark
88970ee29f
pysim.back: fix add_sync_process wrapper to handle signals correctly.
2018-12-14 16:21:53 +00:00
