This fixes the following issues:
- on Python 3.10 and earlier, storing to free variables is now handled
correctly
- on Python 3.11, `_varname_from_oparg` is now used, fixing problems
with cell variables that are also arguments
- on all supported versions, EXTENDED_ARG is now parsed, ensuring proper
handling for long functions
Fixes#792.
This is actually an existing correctness requirement (for the similar
reasons that ValueCastable.as_value() must always return the same
value every time) that for some reason wasn't respected.
See amaranth-lang/rfcs#15 and #784.
Note that this RFC breaks the existing syntax for initializing a view
with a new signal. Instances of `View(layout)` *must* be changed to
`Signal(layout)`.
The __init_subclass__ method fires on class definition rather than use.
It also has the bonus impact that no __new__ method is defined, so the
classes can be correctly detected as mix-in classes by modules such as
enum.
See amaranth-lang/rfcs#4.
This functionality was not explicitly specified in the RFC but it
falls under "anywhere an integer or an enumeration is accepted".
* Reject union initialization with more than one reset value.
* Replace the reset value specified in the class definition with
the one provided during initalization instead of merging.
* Annotations like `s: unsigned(4) = 1` are recognized and
the assigned value is used as the reset value for the implicitly
created `Signal`.
* Base classes inheriting from `Struct` and `Union` without
specifying a layout are recognized.
* Classes that both inherit from a base class with a layout and
specify a layout are rejected.
Mutability of Field isn't specified by the RFC and can cause issues
if the objects stored in Layout subclasses are mutated. There isn't
any reason to do that (the subclasses themselves are mutable and
handle that correctly), so disallow it.
These operators are ignored when they are encountered on LHS, as
the signedness of the assignment target does not matter in Amaranth.
.as_signed() appears on LHS of assigns to signed aggregate fields.
Using floats to represent simulation time internally isn't ideal
instead use 1ps internal units while continuing to use a floating
point based interface for compatibility.
Fixes#535.
A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.
This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.
Fixes#588.
Avoid calling `__getattr__("_ValueCastable__lowered_to")` when
a ValueCastable has custom `__getattr__` implementation; this avoids
the need for downstream code to be aware of this implementataion
detail.
