The build scripts generated by Amaranth are designed to be invoked by
directly running them with any shell (some of them will re-invoke
themselves with `bash` specifically, when it's a toolchain requirement),
and they're not currently marked executable, so there's no shebang.
Add a shebang line to improve compatibility with cases where they are
treated as executables in their own right.
Rather than requiring each additional requested trace to be a signal,
all of the signals in the provided value are added to the GTKW file and
to the VCD file if they are not already there. This improves usability
for `lib.data` as struct fields can now be added to traces.
See #790.
This commit adds an entirely private API for describing formatting of
values that is used in the standard library, in departure from our
standing policy of not using private APIs in the standard library.
This is a temporary measure intended to get the version 0.4 released
faster, as it has been years in the making. It is expected that this
API will be made public in the version 0.5 after going through the usual
RFC process.
This commit only adds VCD lines for fields defined in `lib.data.Layout`
when using `sim.pysim`. The emitted RTLIL and Verilog remain the same.
It is expected that when `sim.cxxsim` lands, RTLIL/Verilog output will
include aliases for layout fields as well.
The value representation API also handles formatting of enumerations,
with no changes visible to the designer. The implementation of
`Signal(decoder=)` is changed as well to use the new API, with full
backwards compatibility and no public API changes.
Co-authored-by: Wanda <wanda@phinode.net>
Although `@property` is the most common case, any descriptors are now
properly supported.
The special casing of methods goes away as they work by having functions
implement the descriptor protocol. (`__get__` has some special behavior
to make this possible.)
This is some of the most cursed code I have ever written, yet it is
obviously necessary.
At the moment there are two issues with assignment of names in pysim:
1. Names are not deduplicated. It is possible (and frequent) for names
to be included twice in VCD output.
2. Names are different compared to what is emitted in RTLIL, Verilog,
or CXXRTL output.
This commit fixes issue (1), and issue (2) will be fixed by the new IR.
