usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
1648 commits 1 branch 0 tags 3.8 MiB
Commit graph

1648 commits

This branch
This branch
All branches
Author SHA1 Message Date
whitequark
8b34602d91 vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly. 
Before this commit, in some cases there will be an inverter, which is
not allowed on an FDCE with IOB attribute set to true, as it will
interfere with packing.
 2019-06-17 15:47:56 +00:00
Alain Péteut
04c07715b4 build.plat: dedent overrides. 2019-06-16 12:40:52 +00:00
whitequark
70bbfecf6d vendor.lattice_ice40: never place an inverter on global buffer output. 
This would make `pin.i` not a global network anymore, which is likely
undesirable if an explicit Attrs(GLOBAL=1) is specified.
 2019-06-14 20:44:02 +00:00
Jean-François Nguyen
01a3101fd3 vendor.xilinx_7series: implement inverters. 2019-06-13 15:14:09 +00:00
Jean-François Nguyen
412781e0c3 vendor.xilinx_spartan6: implement DDR I/O buffers and inverters. 2019-06-13 15:13:31 +00:00
whitequark
2566747061 compat.fhdl.structure: fix Case().makedefault(). 
Fixes #100.
 2019-06-13 03:56:57 +00:00
whitequark
f689b777b4 compat.fhdl.structure: always order default case as the very last. 2019-06-13 03:56:57 +00:00
whitequark
f1174655b1 hdl.ast: tighten assertion in Switch(). 2019-06-13 03:56:57 +00:00
whitequark
6beba3a48b Simplify code by using Signal.like(name_suffix="..") appropriately. 2019-06-12 22:28:45 +00:00
whitequark
e52b15d236 hdl.ast: add name_suffix=".." option to Signal.like(). 
This simplifies creation of related signals with nice names during
metaprogramming, e.g.

  def make_ff(m, sig):
      sig_ff = Signal.like(sig, name_suffix="_ff")
      m.d.sync += sig_ff.eq(sig)
      return sig_ff
 2019-06-12 22:26:57 +00:00
Jean-François Nguyen
3b303c3334 vendor.xilinx_7series: implement DDR I/O buffers. 2019-06-12 19:55:10 +00:00
whitequark
d3ed390b9d vendor.lattice_ice40: fix typo. 2019-06-12 17:38:14 +00:00
whitequark
efb2d773c3 build.{dsl,res,plat}: add PinsN and DiffPairsN. 2019-06-12 14:42:39 +00:00
whitequark
ad1a40c934 hdl.ast: implement values with custom lowering. 2019-06-11 07:01:44 +00:00
whitequark
066dd799e8 back.pysim: check for a clock being added twice. 
This commit adds a best-effort error for a common mistake of adding
a clock driving the same domain twice, such as a result of
a copy-paste error.

Fixes #27.
 2019-06-11 03:54:22 +00:00
whitequark
d2d8c2b8bf back.rtlil: mask memory init values. 
This handles both init values that are too wide, which happens if
their magnitude is too high, or if they're negative.

Fixes #96.
 2019-06-11 03:43:09 +00:00
whitequark
58e39f90ce hdl.mem: coerce memory init values to integers. 
The coercion is carefully chosen to accept (other than normal ints)
instances of e.g. np.int64, but reject instances of e.g. float.
See https://stackoverflow.com/a/48940855/254415 for details.

Fixes #93.
 2019-06-11 03:38:44 +00:00
Simon Kirkby
2423eabc15 lib.cdc: fix typo. 2019-06-09 10:24:01 +00:00
Jean-François Nguyen
d5ba26b174 vendor.xilinx_spartan6: implement. 2019-06-07 08:58:41 +00:00
Jean-François Nguyen
2b3a0e9fa0 vendor.xilinx_7series: fix typos. 2019-06-07 07:33:20 +00:00
whitequark
12e8fe484d build.dsl: fix precondition check in Pins. 2019-06-06 20:40:49 +00:00
Jean-François Nguyen
f26e612899 vendor.xilinx_7series: implement. 2019-06-06 13:22:15 +00:00
whitequark
b45c5119f5 build.res: allow querying frequency of a previously constrained clock. 2019-06-05 12:51:53 +00:00
whitequark
c9879c795b build.{dsl,res,plat}: apply clock constraints to signals, not resources. 
This adds the Clock() build DSL element, and adds a resource manager
function add_clock_constraint() that takes a Pin or a Signal.
Note that not all platforms, in particular not any nextpnr platforms
at the moment, can add constraints on arbitrary signals.

Fixes #86.
 2019-06-05 08:52:30 +00:00
whitequark
ab3f103e5a build.dsl: replace extras= with Attrs(). 
This change proved more tricky than expected due to downstream
dependencies, so it also includes some secondary refactoring.
 2019-06-05 07:02:08 +00:00
whitequark
c52cd72d3e Typos and style fixes. NFC. 2019-06-05 02:48:41 +00:00
whitequark
452c4b380b vendor.lattice_ice40: normalize device names. 
Right now the device name in the board file is just the option
nextpnr uses, but that's overnormalized and doesn't quite match
the chip names used elsewhere. It is even worse for ECP5 in terms
of mismatch with chip names, and for ECP5 we need to support other
toolchains as well, so let's handle this uniformly everywhere.
 2019-06-04 16:09:08 +00:00
whitequark
4379a5d6fe hdl.ir: rephrase elaboratable warning to not look like an error. 2019-06-04 13:11:15 +00:00
whitequark
537d91851d compat.fhdl.module: silence "unused elaboratable" warnings. 2019-06-04 13:09:36 +00:00
whitequark
38917e4523 compat.fhdl.specials: fix platform lowering for TSTriple again. 2019-06-04 13:03:56 +00:00
whitequark
79a3710255 compat.fhdl.specials: fix platform lowering. 
get_tristate only has O/OE; the triple is created by get_input_output.
 2019-06-04 12:26:09 +00:00
whitequark
0cbb743df9 compat.fhdl.module: implement some TODO'd deprecation warnings. 2019-06-04 12:00:02 +00:00
whitequark
3adce21ce3 build.run: fix product extraction to work on Windows. 
Before this commit, it would fail with a "Permission denied" error.
 2019-06-04 11:40:56 +00:00
whitequark
63c4123f6e build.plat: hide executed commands in quiet builds on Windows. 2019-06-04 11:34:18 +00:00
whitequark
1d3e9c8331 build.plat: allow (easily) overriding with an empty string on Windows. 2019-06-04 11:33:51 +00:00
whitequark
39ca0e6fa6 compat.fhdl.module: CompatModule should be elaboratable. 
Fixes #83.
 2019-06-04 11:11:31 +00:00
whitequark
4310254103 build.res: use ConstraintError iff a constraint invariant is violated. 
In particular don't use it for type errors.
 2019-06-04 11:00:11 +00:00
whitequark
51c03ca391 hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}. 2019-06-04 10:26:01 +00:00
whitequark
1b54eb80da vendor.board: split off into nmigen-boards package. 
The iCE40 programmers are also moved, since they're board-specific.
(It looks like iceprog isn't, but it only works with Lattice
evaluation kits.)

Fixes #80.
 2019-06-04 09:52:33 +00:00
whitequark
316ba10207 build.run: simplify using build products locally, e.g. for programming. 2019-06-04 09:13:24 +00:00
whitequark
2763b403f1 build.res: simplify emission of port constraints on individual bits. 2019-06-04 08:39:03 +00:00
whitequark
9f643ce005 Clean up imports. 
This commit:
  * moves lists of universally useful imports from `nmigen` to
    `nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
  * replaces lots of imports from individual parts of `nmigen.hdl`
    with a star import from `nmigen.hdl`;
  * replaces imports in tests with what we expect downstream code
    to use;
  * adds some missing imports in `nmigen.formal`.
 2019-06-04 08:18:50 +00:00
whitequark
3194b5c90b build.run: extract from build.plat. 2019-06-04 07:53:34 +00:00
whitequark
c89c2ce941 vendor.board.tinyfpga_bx: clk16 pin does not have a global buffer. 
Fixes #82.
 2019-06-04 06:43:10 +00:00
whitequark
45d1dc1d54 vendor.board.tinyfpga_bx: fix typo. 2019-06-04 06:20:01 +00:00
whitequark
6426b90e4a vendor.conn.pmod: implement. 
Fixes #79.
 2019-06-03 16:49:59 +00:00
whitequark
3d04122d55 examples: reorganize into examples/basic and examples/board. 2019-06-03 16:17:37 +00:00
whitequark
0fa45b5e14 vendor.board: extract package. 2019-06-03 16:14:59 +00:00
whitequark
2ca0834d41 vendor.tinyfpga_bx: add connectors. 2019-06-03 15:40:57 +00:00
whitequark
7c5461d210 vendor.icestick: add connectors. 2019-06-03 15:15:45 +00:00