whitequark
585514e6ed
hdl.ir: rework named port handling for Instances.
...
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.
While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
2019-04-22 07:46:47 +00:00
whitequark
44711b7d08
hdl.ir: detect elaboratables that are created but not used.
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Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.
Fixes #3 .
2019-04-21 08:52:57 +00:00
whitequark
33f9bd2a1d
hdl.ast: accept Signals with identical min/max bounds.
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And produce a 0-bit signal.
Fixes #58 .
2019-04-21 07:16:59 +00:00
whitequark
ce1eff5464
hdl.rec: implement Record.connect.
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Fixes #31 .
2019-04-21 06:37:08 +00:00
whitequark
611c25f909
hdl.rec: fix slicing of records.
2019-04-19 19:55:39 +00:00
whitequark
dda8f34d39
hdl.xfrm: handle classes that inherit from Record.
2019-04-18 17:06:33 +00:00
whitequark
50fa2516fa
hdl.ast: fix some type checks.
2019-04-10 04:33:44 +00:00
whitequark
0a2a7025a6
hdl.xfrm: allow using FragmentTransformer on any elaboratable.
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Fixes #29 .
2019-04-10 00:23:11 +00:00
whitequark
49eef77c53
hdl: remove deprecated get_fragment() and lower() methods.
2019-04-09 23:53:43 +00:00
whitequark
a74cacdc69
hdl.ast: handle a common typo, such as Signal(1, True).
2019-04-03 14:59:01 +00:00
anuejn
3c95299c4e
hdl.rec: separate record and signal name with __, not _.
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This makes names of signals within records less ambiguous, in case
they themselves have underscores within them.
2019-03-25 14:26:00 +00:00
whitequark
81ee2db163
hdl.ast: fix typo.
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Fixes #49 .
2019-03-25 10:50:39 +00:00
whitequark
e93bf4bf4b
tracer: factor out get_var_name(default=).
2019-03-03 18:21:22 +00:00
whitequark
cac4b10b82
hdl.rec: remove __slots__.
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Left in by mistake.
2019-03-03 18:21:22 +00:00
whitequark
8ee6bd80ff
hdl.ir: raise a more descriptive error on non-elaboratable object.
2019-02-14 20:52:42 +00:00
whitequark
bc5a127fd2
hdl.ast: fix ValueKey for Cat.
2019-01-26 23:25:34 +00:00
whitequark
4948162f33
hdl.ir: rename .get_fragment() to .elaborate().
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Closes #9 .
2019-01-26 02:31:12 +00:00
whitequark
f71e0fffbb
hdl.ast: fix shape calculation for *.
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This was carried over from Migen, and is wrong there too.
Counterexample: 1'sd-1 * 4'sd-4 = 4'sd-4 (but should be 5'sd4).
2019-01-26 00:56:40 +00:00
whitequark
38b3c4af31
hdl.ast: implement shape for modulo operator.
2019-01-19 09:27:56 +00:00
whitequark
5e2b46f727
hdl.ast: add Value.implies.
2019-01-19 08:56:44 +00:00
whitequark
c5d67b0461
hdl.xfrm: mark internal registers used in lowering Sample().
2019-01-19 07:27:32 +00:00
whitequark
b50b47d984
hdl.ast: give Assert and Assume their own src_loc.
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This helps with patterns like `Assert(fsm.ongoing("IDLE"))`, which
would otherwise point into nMigen internals.
2019-01-19 00:08:51 +00:00
whitequark
66466a8a0e
back.rtlil: only emit each AnyConst/AnySeq cell once.
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These are semantically like signals, not like constants.
2019-01-18 01:34:48 +00:00
whitequark
fa8e876356
hdl.ast: allow sampling ClockSignal, ResetSignal.
2019-01-17 05:23:06 +00:00
whitequark
8c96675580
hdl.ast: add Past, Stable, Rose, Fell.
2019-01-17 04:31:27 +00:00
whitequark
198efcad31
hdl.xfrm: add SampleLowerer.
2019-01-17 01:41:02 +00:00
whitequark
b3de114d67
hdl.ast: add Sample.
2019-01-17 01:36:27 +00:00
whitequark
cb2f18ee37
hdl.ast: fix naming of Signal.like() signals when tracer fails.
2019-01-16 17:20:38 +00:00
William D. Jones
77728c2dea
hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children.
2019-01-15 22:52:45 +00:00
William D. Jones
6fdbc3d885
hdl.ast: Add AnyConst and AnySeq value types.
2019-01-15 22:52:45 +00:00
whitequark
b534e92dd5
hdl.ir: allow explicitly requesting flattening.
2019-01-14 17:04:23 +00:00
whitequark
011bf2258e
hdl: make ClockSignal and ResetSignal usable on LHS.
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Fixes #8 .
2019-01-14 15:38:16 +00:00
whitequark
664b4bcb3a
hdl.dsl: cases wider than switch test value are unreachable.
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In 3083c1d6
2019-01-13 08:51:49 +00:00
whitequark
3083c1d6dd
hdl.dsl: accept (but warn on) cases wider than switch test value.
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Fixes #13 .
2019-01-13 08:46:28 +00:00
whitequark
a2b04d71d0
hdl.ast: allow slicing [n:n] into n-bit value.
2019-01-02 18:14:57 +00:00
William D. Jones
f77dc40256
hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children.
2019-01-02 11:17:39 +00:00
William D. Jones
2412650f56
hdl.dsl: Support Assert and Assume where an Assign can occur.
2019-01-02 11:17:39 +00:00
William D. Jones
e6517a33c7
hdl.ast: Add Assert and Assign statements.
2019-01-02 11:17:39 +00:00
whitequark
ea7e19ed5c
hdl.ast: experimentally add Value._as_const.
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Useful for writing e.g. decoders that accept Cat, etc as argument.
2019-01-01 09:50:39 +00:00
whitequark
3c07d8d52c
hdl.rec: include record name in error message.
2019-01-01 03:39:12 +00:00
whitequark
031a9e2616
hdl.rec: use a helpful error on unknown field reference.
2019-01-01 03:35:34 +00:00
whitequark
d78e6c155b
hdl.mem: add DummyPort, for testing and verification.
2019-01-01 03:08:10 +00:00
whitequark
39eb2e8fa7
lib.cdc: fix tests to actually run.
2018-12-29 15:02:44 +00:00
whitequark
92a96e1644
hdl.rec: add basic record support.
2018-12-28 13:22:10 +00:00
whitequark
d66bbb0df8
tracer: factor out get_src_loc().
2018-12-28 01:31:24 +00:00
whitequark
470d66934f
hdl.dsl: add support for fsm.ongoing().
2018-12-27 16:19:01 +00:00
whitequark
de50ccec90
hdl.mem: add missing __all__.
2018-12-27 16:19:01 +00:00
whitequark
35a44f017f
hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.
2018-12-26 12:42:43 +00:00
whitequark
934546e633
hdl.dsl: provide generated values for FSMs.
2018-12-26 12:39:05 +00:00
whitequark
040811c2e5
hdl.ir: add an API for retrieving generated values, like FSM signal.
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This is useful for tests.
2018-12-26 12:35:35 +00:00
