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  • 6ee760e83f build.dsl: Add optional name_suffix to Resource.family. William D. Jones 2019-07-10 11:29:09 -04:00
  • 278b624c66 back.pysim: avoid malformed VCD files when a decoder uses tabs. whitequark 2019-07-10 12:54:59 +00:00
  • 2fa858b003 hdl.ir: make UnusedElaboratable a real warning. whitequark 2019-07-10 12:46:46 +00:00
  • 37f363e338 back.rtlil: add decodings to cases when switching on a signal. whitequark 2019-07-09 19:45:15 +00:00
  • 10e56c75fb back.verilog: run proc_prune for much cleaner output. whitequark 2019-07-09 19:28:09 +00:00
  • 00c5209a47 hdl.{ast,dsl},back.rtlil: track source locations for switch cases. whitequark 2019-07-09 19:18:02 +00:00
  • 62b3e36612 tracer: add PyPy support to get_var_name(). Jacob Lifshay 2019-07-09 00:29:01 -07:00
  • 367ad5aee7 build.dsl: add Resource.family abstraction. whitequark 2019-07-09 02:44:03 +00:00
  • 7b4fbf8e01 build.{dsl,res}: allow platform-dependent attributes using callables. whitequark 2019-07-08 11:15:04 +00:00
  • 0ab0a74ec1 hdl.rec: respect modifications to signals in Record.like(). whitequark 2019-07-08 10:59:15 +00:00
  • bfbeca4584 back.rtlil: don't name-prefix signals connected to instance ports. whitequark 2019-07-08 10:48:07 +00:00
  • 0b844da4cf build.{dsl,res}: allow removing attributes from subsignals. whitequark 2019-07-08 10:41:45 +00:00
  • f0c1c2cfeb build.dsl: allow assertions on subsignal widths. whitequark 2019-07-08 10:32:41 +00:00
  • a7fbff94d8 hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain. whitequark 2019-07-08 10:26:49 +00:00
  • 345a26b04b test: fix Travis. whitequark 2019-07-08 10:20:24 +00:00
  • 5c63177fc2 test: generate examples to verilog as part of unit tests. whitequark 2019-07-08 10:12:15 +00:00
  • c14d074fcc examples/basic/ctr_ce: fix outdated syntax. whitequark 2019-07-08 10:00:16 +00:00
  • 447bfa6ad5 compat.genlib.fsm: fix after commit dac62754. whitequark 2019-07-08 10:03:20 +00:00
  • ec7fcd3697 hdl.xfrm: don't overwrite source locations on ClockDomain signals. whitequark 2019-07-08 09:57:14 +00:00
  • 8c9fdf907f hdl.{dsl,mem,xfrm}: inject appropriate source locations. whitequark 2019-07-08 09:50:07 +00:00
  • 710a8d0bc1 back.rtlil: ignore empty source locations. whitequark 2019-07-08 09:33:01 +00:00
  • dac6275493 hdl.ast: use keyword-only arguments as appropriate. whitequark 2019-07-08 09:23:33 +00:00
  • 70f3563b5f back.rtlil: attach source locations to switches, not processes. whitequark 2019-07-08 09:09:40 +00:00
  • 2492f490f5 back.rtlil: use a more principled approach to attributes. NFC. whitequark 2019-07-08 08:57:36 +00:00
  • 31c54d32ef vendor.xilinx_7series: generate also binary bitfile. Alain Péteut 2019-07-07 23:36:32 +02:00
  • b404d603fb vendor.xilinx_spartan_3_6: Add Spartan3A family support. William D. Jones 2019-07-07 16:44:48 -04:00
  • cb02a452e9 vendor.lattice_ecp5: don't leave LUT inputs disconnected. whitequark 2019-07-07 02:30:56 +00:00
  • da1f58b7ae hdl.dsl: further clarify error message for incorrect nesting. whitequark 2019-07-07 01:03:59 +00:00
  • cb8be4a1b0 hdl.dsl: clarify error message for incorrect nesting. whitequark 2019-07-07 00:59:57 +00:00
  • 3388b5b085 hdl.dsl: gracefully handle FSM with no states. whitequark 2019-07-07 00:59:34 +00:00
  • 146f3cb684 build.plat: source a script with toolchain environment. whitequark 2019-07-07 00:41:03 +00:00
  • 744154ebb5 build.run: only use os.path on the target OS. whitequark 2019-07-07 00:18:56 +00:00
  • ba64eb2037 build.run: make BuildProducts abstract, add LocalBuildProducts. whitequark 2019-07-07 00:07:55 +00:00
  • 1ee21d2007 build.plat, vendor.*: don't join strings passed as _opts overrides. whitequark 2019-07-06 23:09:46 +00:00
  • b6b9f0fc21 build.run: make sure BuildProducts._root is not easily accessible. whitequark 2019-07-06 18:44:25 +00:00
  • 2829d04033 vendor.xilinx_{7series,spartan6}: Support extra VHDL files. Staf Verhaegen 2019-07-04 17:13:56 +02:00
  • 2e4cc47fcb hdl.dsl: fix src_loc_at for FSM state signal. whitequark 2019-07-03 16:34:31 +00:00
  • 82903e493a back.rtlil: emit \src attributes for processes via Switch and Assign. whitequark 2019-07-03 16:27:54 +00:00
  • e351e27206 hdl.ast: fix src_loc_at for Mux(). whitequark 2019-07-03 15:25:14 +00:00
  • b471e33d7f build.res: detect physical conflicts earlier. whitequark 2019-07-03 15:07:44 +00:00
  • 7059cb4931 hdl.rec: thread src_loc_at to all inner Signals and Records. whitequark 2019-07-03 14:49:20 +00:00
  • 33f21628bb vendor: give names to IO buffer instances. whitequark 2019-07-03 14:43:03 +00:00
  • 5800f00776 hdl.rec: accept Record(src_loc_at=...). whitequark 2019-07-03 14:35:48 +00:00
  • 668ff40a75 compat.fhdl.specials: mark CompatMemory as Elaboratable. whitequark 2019-07-03 13:28:57 +00:00
  • eeb6aca93d compat.fhdl.specials: use "sync" as default domain, not "sys". whitequark 2019-07-03 13:25:12 +00:00
  • c98b8f7c07 compat.fhdl.specials: fix Memory.get_port() after 94e8f479. whitequark 2019-07-03 13:24:00 +00:00
  • 9eb81609d6 compat.fhdl.structure: fix If/Elif/Else after 32446831. whitequark 2019-07-03 13:19:15 +00:00
  • 9a1048af50 lattice_ecp5: fix get_input Sebastien Bourdeauducq 2019-07-03 10:25:32 +08:00
  • 0ab215e5ed hdl.ast: recognize a Enum used as decoder and format it better. whitequark 2019-07-02 19:02:16 +00:00
  • 7cc0b8cbf0 hdl.mem: fix naming of registers inside unnamed memories. whitequark 2019-07-02 18:37:02 +00:00
  • 20553b1478 build.plat: add iter_extra_files method. Alain Péteut 2019-07-02 10:44:12 +02:00
  • ea25806971 back.rtlil: emit \sig$next wires instead of \$next\sig. NFC. whitequark 2019-07-02 18:06:50 +00:00
  • dd5e513e42 back.rtlil: do not emit $next wires for comb signals. whitequark 2019-07-02 18:05:34 +00:00
  • 6b843b5be6 hdl.rec: implement slicing by component names. whitequark 2019-07-02 17:44:55 +00:00
  • 34f110100a hdl.rec: implement Record.like. whitequark 2019-07-02 17:35:00 +00:00
  • b67f5cfa65 vendor.xilinx_7series: read extra .xdc files. Alain Péteut 2019-07-02 09:47:40 +02:00
  • 94e8f479a5 hdl.mem: use read_port(domain="comb") for asynchronous read ports. whitequark 2019-07-01 19:56:49 +00:00
  • f75a0163f9 back.rtlil: fix Array regression in 32446831. whitequark 2019-07-01 01:53:56 +00:00
  • 9c54d0c061 back.pysim: create unique ResetSynchronizer internal domains. whitequark 2019-06-28 08:34:02 +00:00
  • 300d47ca2e back.pysim: override ResetSynchronizer implementation. whitequark 2019-06-28 07:49:14 +00:00
  • 779f3ee906 lib.cdc: avoid interior clock domains in ResetSynchronizer. whitequark 2019-06-28 07:34:10 +00:00
  • 21379dd44b lib.cdc: eliminate no_retiming attributes. whitequark 2019-06-28 07:22:54 +00:00
  • 6454378fe7 vendor.lattice_ice40: fix instance of negedge FF due to a typo. whitequark 2019-06-28 07:05:10 +00:00
  • 1609a5ba54 build.plat: fix dedent overrides. Alain Péteut 2019-06-27 20:56:37 +02:00
  • f0a7f84a6d README: tone down the instability warning to reflect current status. whitequark 2019-06-28 05:10:29 +00:00
  • 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. whitequark 2019-06-28 04:37:08 +00:00
  • 48d4ee4031 hdl.ir, back.rtlil: allow specifying attributes on instances. whitequark 2019-06-28 04:14:38 +00:00
  • 2b92f12016 examples: add concise UART example. whitequark 2019-06-27 04:51:45 +00:00
  • 6f4e3156d8 back.pysim: fix scope screwup. whitequark 2019-06-26 05:22:09 +00:00
  • 2f7e52369c compat.fhdl.structure: fix typo. whitequark 2019-06-25 21:53:08 +00:00
  • b1af0601fa compat.fhdl.structure: simplify handling of default case. whitequark 2019-06-25 21:52:03 +00:00
  • e5e23644a4 hdl.{ast,dst}: directly represent RTLIL default case. whitequark 2019-06-25 17:53:09 +00:00
  • f60ceb349b vendor.xilinx_{spartan6,7series}: speedgrade→speed. whitequark 2019-06-25 15:51:52 +00:00
  • 0a145ed2d9 vendor.lattice_ecp5: implement. whitequark 2019-06-25 15:47:53 +00:00
  • 56fe329e0c README: update nMigen libs paragraph Sebastien Bourdeauducq 2019-06-24 10:05:25 +08:00
  • 67c06b4540 README: add clarification about HLS Sebastien Bourdeauducq 2019-06-24 10:00:31 +08:00
  • 23ed888857 vendor.lattice_ice40: use different --package for 4k devices. whitequark 2019-06-19 06:09:08 +00:00
  • b3c5ff7e95 vendor.xilinx_7series: fix IOB packing. Jean-François Nguyen 2019-06-17 20:01:26 +02:00
  • 3fc5f170e6 vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly. whitequark 2019-06-15 16:07:40 +00:00
  • 2a8e7bc6f2 vendor.xilinx_{7series,spartan6}: cleanup. NFC. whitequark 2019-06-15 16:01:37 +00:00
  • 8b34602d91 vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly. whitequark 2019-06-15 15:55:10 +00:00
  • 04c07715b4 build.plat: dedent overrides. Alain Péteut 2019-06-16 14:06:39 +02:00
  • 70bbfecf6d vendor.lattice_ice40: never place an inverter on global buffer output. whitequark 2019-06-14 20:44:02 +00:00
  • 01a3101fd3 vendor.xilinx_7series: implement inverters. Jean-François Nguyen 2019-06-13 14:33:24 +02:00
  • 412781e0c3 vendor.xilinx_spartan6: implement DDR I/O buffers and inverters. Jean-François Nguyen 2019-06-12 16:56:05 +02:00
  • 2566747061 compat.fhdl.structure: fix Case().makedefault(). whitequark 2019-06-13 03:54:46 +00:00
  • f689b777b4 compat.fhdl.structure: always order default case as the very last. whitequark 2019-06-13 03:52:04 +00:00
  • f1174655b1 hdl.ast: tighten assertion in Switch(). whitequark 2019-06-13 03:56:49 +00:00
  • 6beba3a48b Simplify code by using Signal.like(name_suffix="..") appropriately. whitequark 2019-06-12 22:28:45 +00:00
  • e52b15d236 hdl.ast: add name_suffix=".." option to Signal.like(). whitequark 2019-06-12 22:21:23 +00:00
  • 3b303c3334 vendor.xilinx_7series: implement DDR I/O buffers. Jean-François Nguyen 2019-06-11 19:57:55 +02:00
  • d3ed390b9d vendor.lattice_ice40: fix typo. whitequark 2019-06-12 17:38:14 +00:00
  • efb2d773c3 build.{dsl,res,plat}: add PinsN and DiffPairsN. whitequark 2019-06-12 14:42:39 +00:00
  • ad1a40c934 hdl.ast: implement values with custom lowering. whitequark 2019-06-11 07:01:44 +00:00
  • 066dd799e8 back.pysim: check for a clock being added twice. whitequark 2019-06-11 03:54:22 +00:00
  • d2d8c2b8bf back.rtlil: mask memory init values. whitequark 2019-06-11 03:43:09 +00:00
  • 58e39f90ce hdl.mem: coerce memory init values to integers. whitequark 2019-06-11 03:38:44 +00:00
  • 2423eabc15 lib.cdc: fix typo. Simon Kirkby 2019-06-09 18:24:01 +08:00
  • d5ba26b174 vendor.xilinx_spartan6: implement. Jean-François Nguyen 2019-06-07 00:48:51 +02:00
  • 2b3a0e9fa0 vendor.xilinx_7series: fix typos. Jean-François Nguyen 2019-06-07 00:54:52 +02:00