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  • 54fb999c99 back.pysim: implement ArrayProxy. whitequark 2018-12-15 19:37:36 +0000
  • 80c5343600 hdl.ast: implement Array and ArrayProxy. whitequark 2018-12-15 17:16:22 +0000
  • 1580b6e542 Lower Python version requirement to 3.6. whitequark 2018-12-15 17:03:23 +0000
  • c6e7a93717 hdl: appropriately rename tests. NFC. whitequark 2018-12-15 16:13:53 +0000
  • f603b735e8 hdl.ast: improve ClockSignal, ResetSignal documentation. whitequark 2018-12-15 14:58:31 +0000
  • 790eb05a92 Rename fhdl→hdl, genlib→lib. whitequark 2018-12-15 14:23:42 +0000
  • b5a1efa0c8 Move star imports to make from nmigen import * usable. whitequark 2018-12-15 14:20:10 +0000
  • ad3c88852f doc: fix some Markdown awkwardness. whitequark 2018-12-15 12:07:56 +0000
  • cc96a7ecfa doc: update COMPAT_SUMMARY to reflect actual status. whitequark 2018-12-15 12:04:52 +0000
  • 1f10bd96b9 Determine Migen's API surface and document compatibility summary. whitequark 2018-12-15 11:51:09 +0000
  • b70340c0da pyback.sim: test Slice, Cat, Repl. whitequark 2018-12-15 10:09:14 +0000
  • db4600d52b fhdl.ast, back.pysim: implement shifts. whitequark 2018-12-15 09:58:30 +0000
  • 46f5addf05 fhdl.ast: refactor Operator.shape(). NFC. whitequark 2018-12-15 09:46:20 +0000
  • 3a8685c352 Consistently use '{!r}' in and only in TypeError messages. whitequark 2018-12-15 09:31:58 +0000
  • f9f7921959 fhdl.ir: test iter_comb(), iter_sync() and iter_signals(). whitequark 2018-12-15 09:26:36 +0000
  • f5e8c9033d fhdl.ir: fix incorrect uses of positive to say non-negative. whitequark 2018-12-15 09:19:26 +0000
  • 9010805040 compat.fhdl.structure: handle If/Elif with multi-bit condition. whitequark 2018-12-15 00:10:54 +0000
  • ecea721f43 compat.fhdl.module: allow adding native submodules to compat modules. whitequark 2018-12-14 23:40:15 +0000
  • 1c7b43ea49 Fix deprecations in Python 3.7. whitequark 2018-12-14 23:56:26 +0000
  • 7108111ad0 back.pysim: preserve process locations through add_sync_process(). whitequark 2018-12-14 23:27:36 +0000
  • c4ba5a3915 fhdl.ast: clean up stub error messages. NFC. whitequark 2018-12-14 22:54:07 +0000
  • 2001359b66 fhdl.ir: automatically flatten hierarchy to resolve driver conflicts. whitequark 2018-12-14 22:47:58 +0000
  • 579feaba4e fhdl.ir: Fragment.{drive→add_driver} whitequark 2018-12-14 20:58:29 +0000
  • 0015713bfb back.pysim: count delta cycles separately to avoid clock drift. whitequark 2018-12-14 20:52:41 +0000
  • a6a8703a0e back.pysim: simplify. whitequark 2018-12-14 20:26:52 +0000
  • 7e3cf26cf8 back.pysim: revert 70ebc6f2. whitequark 2018-12-14 19:46:08 +0000
  • 71304c9fe7 back.pysim: fix implicit boolean conversion. whitequark 2018-12-14 19:08:06 +0000
  • fe5fb34fae back.pysim: squash one level of hierarchy. whitequark 2018-12-14 18:53:21 +0000
  • 70ebc6f2c1 back.pysim: implement blocking assignment semantics correctly. whitequark 2018-12-14 18:47:12 +0000
  • 120d817123 back.pysim: undriven sync signals should return to previous value. whitequark 2018-12-14 17:25:48 +0000
  • 4f5b4a9bf4 back.pysim: in simulator sync processes, start by waiting for a tick. whitequark 2018-12-14 17:05:11 +0000
  • e230383aac back.pysim: make initial phase configurable. whitequark 2018-12-14 16:46:16 +0000
  • 0ef5ced492 compat.sim: match clock period. whitequark 2018-12-14 16:39:52 +0000
  • 17d26c8329 compat: add run_simulation shim. whitequark 2018-12-14 16:22:18 +0000
  • 88970ee29f pysim.back: fix add_sync_process wrapper to handle signals correctly. whitequark 2018-12-14 16:21:53 +0000
  • 3bc3647380 compat.fhdl.module: fix specials. whitequark 2018-12-14 16:14:08 +0000
  • 3b23645fb7 compat: add fhdl.specials.TSTriple shim. whitequark 2018-12-14 16:00:10 +0000
  • 7200346249 genlib.io: import TSTriple from Migen. whitequark 2018-12-14 16:09:26 +0000
  • 50ba443f92 fhdl.ast: fix Switch with constant test. whitequark 2018-12-14 16:07:25 +0000
  • a0d555a9fc compat: add genlib.cdc.MultiReg shim. whitequark 2018-12-14 15:59:49 +0000
  • baba47251c compat.fhdl.module: update deprecation messages. whitequark 2018-12-14 16:00:31 +0000
  • 9307a31678 back.pysim: Simulator({gtkw_signals→traces}=). whitequark 2018-12-14 15:23:22 +0000
  • e3f32a1faf back.pysim: better naming. NFC. whitequark 2018-12-14 15:21:13 +0000
  • 68f8dabb29 Travis: install pyvcd. whitequark 2018-12-14 14:47:03 +0000
  • 474d46ced8 back.pysim: implement most operators and add tests. whitequark 2018-12-14 14:21:22 +0000
  • d9aaf0114b back.pysim: close .vcd/.gtkw files on context manager exit. whitequark 2018-12-14 13:59:03 +0000
  • 1655b59d1b back.pysim: show more legible names for processes in errors. whitequark 2018-12-14 13:50:19 +0000
  • 625c55a3b8 back.pysim: throw exceptions back at processes. whitequark 2018-12-14 13:43:25 +0000
  • 654722ce14 back.pysim: add gtkw traces even more robustly. whitequark 2018-12-14 13:43:08 +0000
  • 7d3f7f277a back.pysim: accept (and evaluate) generator functions. whitequark 2018-12-14 13:30:09 +0000
  • 7fc9f98b98 back.pysim: skip VCD signal population if VCD is not requested. whitequark 2018-12-14 13:25:51 +0000
  • 3ad79ec690 back.pysim: allow processes to evaluate expressions. whitequark 2018-12-14 13:21:58 +0000
  • 151d079f01 fhdl.ir: oops, we defined DomainError twice. whitequark 2018-12-14 12:59:54 +0000
  • dd00b5e2d6 back.pysim: more general clean-up. whitequark 2018-12-14 12:42:39 +0000
  • 1b7f8c7950 back.pysim: general clean-up. whitequark 2018-12-14 12:21:48 +0000
  • 105113f1d8 back.pysim: accept any valid assignments from processes. whitequark 2018-12-14 12:18:41 +0000
  • 240a40c2c2 back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw. whitequark 2018-12-14 10:57:13 +0000
  • 7d91dd56c8 fhdl.xfrm: implement DomainLowerer. whitequark 2018-12-14 10:56:53 +0000
  • b34c1a9ad0 back.pysim: undriven comb signals should return to reset value. whitequark 2018-12-14 09:12:38 +0000
  • b58715c5dc ast, back.pysim: allow specifying user-defined decoders for signals. whitequark 2018-12-14 09:02:29 +0000
  • bb843cb40c back.pysim: fix completely broken codegen for Switch. whitequark 2018-12-14 08:51:36 +0000
  • 6aefd0c04c back.pysim: raise an exception if delta cycles blow a process deadline. whitequark 2018-12-14 08:10:21 +0000
  • a10791e160 back.pysim: if requested, write a gtkw file with a useful preset. whitequark 2018-12-14 08:04:29 +0000
  • cb998d891b back.pysim: explain how delta cycles work. whitequark 2018-12-14 07:26:26 +0000
  • e4d08d2855 back.pysim: delay clock processes by one half period. whitequark 2018-12-14 05:17:43 +0000
  • 3bb7a87e0f back.pysim: implement "sync processes", like migen.sim generators. whitequark 2018-12-14 05:13:58 +0000
  • d791b77cc8 back.pysim: allow suspending processes until a tick in a domain. whitequark 2018-12-14 04:33:06 +0000
  • 3e59d857e1 back.pysim: use bare ints for signal values (-5% runtime). whitequark 2018-12-14 03:05:57 +0000
  • 55e729f68a setup: add missing import. whitequark 2018-12-14 02:32:37 +0000
  • b09f4b10ee back.pysim: collect handlers before running (-5% runtime). whitequark 2018-12-13 18:34:44 +0000
  • a7ebc02bdd back.pysim: allow multiple registered handlers per signal. whitequark 2018-12-13 18:28:11 +0000
  • 6a4004ef8d back.pysim: fix handling of process termination. whitequark 2018-12-13 18:17:58 +0000
  • fb27c2520b back.pysim: new simulator backend (WIP). whitequark 2018-12-13 18:00:05 +0000
  • 71f1f717c4 fhdl.cd: rename ClockDomain signals together with domain. whitequark 2018-12-13 15:24:55 +0000
  • 07c818e077 fhdl.ir: move Fragment prepare logic from back.rtlil. whitequark 2018-12-13 14:33:39 +0000
  • ac498414ab back.verilog: remove debug code. whitequark 2018-12-13 13:42:54 +0000
  • 90f1503c91 fhdl.ir: record port direction explicitly. whitequark 2018-12-13 13:12:31 +0000
  • 6251c95d4e compat.genlib.fsm: import/wrap Migen code. whitequark 2018-12-13 12:40:14 +0000
  • 9661e897e6 fhdl.ir: a subfragment's input that we don't drive is also our input. whitequark 2018-12-13 11:50:56 +0000
  • bb04c9e0da fhdl, back: trace and emit source locations of values. whitequark 2018-12-13 11:35:20 +0000
  • 859c2dbcf0 back.rtlil: never give subfragment cells names starting with $. whitequark 2018-12-13 11:30:16 +0000
  • b150f1915d fhdl.ir: don't crash propagataing ports in empty fragments. whitequark 2018-12-13 11:25:49 +0000
  • 72257b6935 fhdl.ir: implement clock domain propagation. whitequark 2018-12-13 11:01:03 +0000
  • fde2471963 fhdl.ir: remove iter_domains(). whitequark 2018-12-13 10:18:57 +0000
  • f4340c19bb fhdl: cd_name→domain. whitequark 2018-12-13 10:15:01 +0000
  • c5087edfa5 fhdl.cd: add tests. whitequark 2018-12-13 09:19:16 +0000
  • 9bee90f1bd fhdl.xfrm: implement DomainRenamer. whitequark 2018-12-13 08:57:14 +0000
  • 8963ab5d9f fhdl.xfrm: add test for ControlInserter with subfragments. whitequark 2018-12-13 08:45:10 +0000
  • 19aa404628 fhdl.xfrm: add tests for ResetInserter, CEInserter. whitequark 2018-12-13 08:39:02 +0000
  • b1a89ef5fd fhdl.ir: add tests for port propagation. whitequark 2018-12-13 08:09:39 +0000
  • c60392595b Set up Travis CI. whitequark 2018-12-13 07:50:12 +0000
  • 1f1aa7f468 Add LICENSE. whitequark 2018-12-13 07:51:43 +0000
  • 48330f8742 setup: check Python version. whitequark 2018-12-13 07:47:07 +0000
  • a797e27573 fhdl.dsl: add tests for lowering. 99% branch coverage. whitequark 2018-12-13 07:33:56 +0000
  • d2e2d00e45 fhdl.cd: rename ClockDomain.{reset→rst}. whitequark 2018-12-13 07:27:27 +0000
  • e0a81edf4d fhdl.dsl: add tests for submodules. whitequark 2018-12-13 07:24:28 +0000
  • 932f1912a2 fhdl.dsl: use less error-prone Switch/Case two-level syntax. whitequark 2018-12-13 07:11:06 +0000
  • f70ae3bac5 fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else. whitequark 2018-12-13 06:06:51 +0000
  • 5b8708017e fhdl.ast: fix Switch._?hs_signals() for switch without statements. whitequark 2018-12-13 05:00:44 +0000
  • 4e32f6b8de back.verilog: detect undriven public wires using Yosys. whitequark 2018-12-13 04:51:15 +0000