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  • 2356e8d06b build.plat: Fix toolchain_prepare interface breakage. Wanda 2024-02-28 13:13:46 +01:00
  • f2dab705ee lib.io: Expose Pin path and name as attributes. Wanda 2024-02-28 12:43:12 +01:00
  • 1dd2e6150c lib.io: Add missing __repr__ to signature type. Wanda 2024-02-28 10:06:19 +01:00
  • 8af9fe2606 lib.memory: Add missing __eq__ to signature types. Wanda 2024-02-28 09:56:34 +01:00
  • c6bc9b47ef hdl.ir: add IOBufferInstance. Wanda 2024-02-12 15:11:42 +01:00
  • 85bb5ee77c hdl._dsl: Change FSM codegen to avoid mutating AST nodes. Wanda 2024-02-27 15:03:48 +01:00
  • f524dd041a lib.io, build.res: Make Pin and related objects interfaces. Wanda 2024-02-27 10:42:57 +01:00
  • c30585b47b back.rtlil: Emit proper source location for port-signals. Wanda 2024-02-27 11:44:06 +01:00
  • 1cb9d43841 back.rtlil: Remove code allowing internal yosys cells in Instance. Wanda 2024-02-27 11:20:33 +01:00
  • 6dc7c2718c docs/guide: fix a bunch of TODOs. Catherine 2024-02-27 09:03:32 +00:00
  • 77e41cc88a docs: add stub stdlib/memory, mark guide as done. Catherine 2024-02-26 19:38:40 +00:00
  • 751e0f4b57 ir: kill Fragment.ports Wanda 2024-02-11 12:07:45 +01:00
  • a725282751 sim.pysim: Only close VCD/GTKW files if we opened them ourselves. Wanda 2024-02-27 04:10:41 +01:00
  • fc81ff17f7 hdl._ir: Improve driver-driver conflict message. Wanda 2024-02-27 04:26:56 +01:00
  • ccf87c62e4 back.rtlil: strip \ from names added to name_map. Wanda 2024-02-27 03:02:44 +01:00
  • a586df89ad lib.wiring.connect: diagnostic when no connection made. Amelia Cuss 2024-02-23 16:26:46 +11:00
  • 09029cdd91 hdl._ir: remember origins of a fragment during elaboration. Catherine 2024-02-13 14:54:54 +00:00
  • c40cfc9fb5 lib.enum: honor enum.nonmember. Amelia Cuss 2024-02-19 18:45:44 +11:00
  • 890e099ec3 Implement RFC 45: Move hdl.Memory to lib.Memory. Wanda 2024-02-14 11:27:39 +01:00
  • 6d65dc1366 hdl, back.rtlil: track and emit module/submodule locations. Wanda 2024-02-16 16:16:26 +01:00
  • 188eb8d453 back.rtlil: emit wire signedness according to Signal signedness. Wanda 2024-02-16 22:48:54 +01:00
  • 6058ad35cf hdl._ast: make Shape immutable and hashable. Wanda 2024-02-16 15:27:27 +01:00
  • 24a392887a Implement RFC 43: Rename reset= to init=. Wanda 2024-02-14 07:13:12 +01:00
  • b30c87fa3e pyproject: suppress superfluous warning. Catherine 2024-02-15 19:50:31 +00:00
  • 52842ee524 docs: fix link rot. Catherine 2024-02-15 19:35:21 +00:00
  • e3324e1456 hdl._dsl: fix using 0-width Switch with integer keys. Wanda 2024-02-14 00:04:56 +01:00
  • 5ffb48b5fb hdl._ast: fix using 0-width Switch with integer keys. Wanda 2024-02-13 23:48:59 +01:00
  • 0ecd06a7e5 sim: fix using 0-width Switch. Wanda 2024-02-14 00:10:29 +01:00
  • 8033ddf05e pyproject: change yosys-yowasp requirement to match RTLIL backend. Wanda 2024-02-14 07:19:39 +01:00
  • 353a8ce7e3 README: add the full list of supported AMD devices. Wanda 2024-02-13 22:42:14 +01:00
  • 4a8dd808c3 Ensure we build sensible sdists. Catherine 2024-02-13 12:09:14 +00:00
  • 8677ced404 Update README. Catherine 2024-02-13 12:03:18 +00:00
  • 0eac9c3fd0 CI: verify package metadata on all builds. Catherine 2024-02-13 12:03:10 +00:00
  • 841ab94a76 CI: publish packages automatically. Catherine 2024-02-13 11:10:30 +00:00
  • b9c9948038 docs: use :py: role for inline Python code, not :pc:. Catherine 2024-02-13 10:31:44 +00:00
  • 3cb5f63aba _toolchain.yosys: add JavaScript (Pyodide) support. Catherine 2024-02-11 17:24:23 +00:00
  • 9aebf49565 sim.pysim: only import pyvcd when needed. Catherine 2024-02-11 17:14:51 +00:00
  • 5797643c9c docs: remove leftover TODO and warning from #1003, fix matches docs. Wanda 2024-02-12 23:17:50 +01:00
  • a0c8b18546 vendor._intel: use dff instead of $dff. Wanda 2024-02-13 06:57:22 +01:00
  • 3867623727 docs/reference: describe out-of-bounds behavior of bit_select/word_select. Catherine 2024-02-13 05:40:05 +00:00
  • 2dea83cffd docs/reference: minor fixes. Catherine 2024-02-13 04:47:25 +00:00
  • 1dc1d2d709 vendor.lattice_ice40: use SB_DFF instead of $dff. Wanda 2024-02-13 06:37:04 +01:00
  • eebb6ec3bb back.verilog: require Yosys 0.38. Catherine 2024-02-13 04:58:26 +00:00
  • 0da439cce1 hdl._ast: deprecate ValueCastable.lowermethod. Wanda 2024-02-13 05:21:39 +01:00
  • e2fd819742 hdl._ast: fix shift_right and as_signed edge cases. Wanda 2024-02-13 05:31:51 +01:00
  • 0056e982c5 docs/reference: document Value, ValueCastable, ValueLike. Catherine 2024-02-13 02:09:52 +00:00
  • 4a3a9a90e8 hdl._nir: implement __repr__ on NIR classes. Wanda 2024-02-13 02:02:33 +01:00
  • 4014f6429c Implement RFC 27 amendment: deprecate add_sync_process, not add_process. Wanda 2024-02-08 17:53:17 +01:00
  • 2d42d649ee tests: stop using implicit ports. Wanda 2024-02-12 01:15:50 +01:00
  • 18e5bcd6f7 hdl._nir: fix docstring typos. Wanda 2024-02-11 17:12:49 +01:00
  • 84709e2f00 hdl: remove ValueKey, ValueDict, ValueSet. Catherine 2024-02-11 13:43:53 +00:00
  • 6f44438e58 hdl._ir,hdl._nir,back.rtlil: new intermediate representation. Catherine 2023-08-21 05:23:15 +00:00
  • 78981232d9 hdl.xfrm: add assignment legalizer. Catherine 2023-08-21 05:22:33 +00:00
  • 10117607a3 build.plat: fix toolchain environment variable check, #2. Catherine 2024-02-11 08:15:04 +00:00
  • 05ac36751a sim: prefix fields with \. Wanda 2024-02-09 22:04:19 +01:00
  • 45dbce13df hdl: consistently use "comb" for combinatorial domain. Wanda 2024-02-09 20:27:25 +01:00
  • b6c5294e50 hdl.MemoryInstance: refactor and add first-class simulation support. Wanda 2024-02-04 08:15:29 +01:00
  • f4daf74634 sim: Add tests for memory access. Wanda 2024-02-03 17:16:33 +01:00
  • 83a9149c4c CI: Update actions to Node 20. Catherine 2024-02-09 13:47:37 +00:00
  • 6e06fc013f hdl.ir: associate statements with domains. Wanda 2024-02-09 01:53:45 +01:00
  • 09854fa775 hdl.ast: make it impossible to construct *Castable instances. Wanda 2024-02-09 03:09:42 +01:00
  • ace7aea375 lib.wiring: track member source locations. Catherine 2024-02-08 12:57:11 +00:00
  • 78b90fbafa build.plat,vendor: fix toolchain environment variable check. Catherine 2024-02-08 05:39:58 +00:00
  • d8f70be4d9 xilinx: use FDPE instances to implement get_async_ff_sync() Daniel Estévez 2024-02-08 11:53:23 +01:00
  • 9e75962c35 Implement RFC 27: Testbench processes for the simulator. Catherine 2020-10-20 01:54:24 +00:00
  • f48b8650c4 sim: fix simulation loop when process catches an injected exception. Wanda 2024-02-06 19:43:47 +01:00
  • 15b6068c57 Remove features deprecated in past releases. Catherine 2024-02-06 15:49:13 +00:00
  • 5e2f3b7992 Implement RFC 42: Const from shape-castable. Vegard Storheil Eriksen 2024-01-30 23:05:15 +01:00
  • 089213e19f Implement RFC 46: Change Shape.cast(range(1)) to unsigned(0). Wanda 2024-02-03 03:13:51 +01:00
  • 1fe7bd010f hdl: remove subclassing of AnyValue and Property. Catherine 2024-02-05 05:45:45 +00:00
  • 115954b4d9 lib.fifo: add Memory as submodules instead of its ports. [NFC] Wanda 2024-01-31 22:08:18 +01:00
  • b5f0295bf4 docs/changes: mention removal of Repl. Catherine 2024-01-31 03:16:52 +00:00
  • 357ffb680c hdl: remove Repl per RFC 10. Catherine 2024-01-31 02:55:57 +00:00
  • 4da8adf7ba back.rtlil: remove _SyncBuilder. NFC Catherine 2024-01-31 02:42:21 +00:00
  • 572a60d838 hdl: add missing compatibility shims. Catherine 2024-01-31 01:59:20 +00:00
  • 1506f08b81 sim: use Value.cast on traces. Wanda 2024-01-31 00:07:33 +01:00
  • ea3d6c9557 docs/reference: document compat guarantee, importing, shapes. Catherine 2024-01-30 01:44:07 +00:00
  • c9b87a4fc5 docs: lang.rst→guide.rst, add reference.rst. Catherine 2024-01-29 19:26:24 +00:00
  • 5dd1223cf8 amaranth.hdl: start all private names with an underscore. Catherine 2024-01-30 16:43:33 +00:00
  • cf83193bf9 amaranth.hdl: rename internal modules to begin with an underscore. Catherine 2024-01-30 16:49:14 +00:00
  • e88ff1335e docs/start: update to track changes in the language. Catherine 2024-01-30 03:16:32 +00:00
  • 8678d5fa14 hdl.dsl: warn if a case is defined after a default case. Catherine 2024-01-30 02:49:09 +00:00
  • e9299ccd0e hdl.ast: change warning on out-of-range reset to an error, improve it. Wanda 2024-01-29 19:18:18 +01:00
  • 8501d9dd73 docs/changes: fix formatting. Catherine 2024-01-29 19:28:56 +00:00
  • fc7c86bbe6 docs/changes: link to docs for past releases. Catherine 2024-01-29 19:22:14 +00:00
  • 65d77f03fe back.verilog: forbid Yosys version range with dangling else bug. Catherine 2024-01-23 03:33:36 +00:00
  • 0ea2aa6b69 docs/lang: document arrays. Catherine 2024-01-22 22:44:32 +00:00
  • 53f7b628b3 docs/lang: document instances. Catherine 2024-01-22 22:24:02 +00:00
  • a5dd63246c docs/lang: document domain renaming. Catherine 2024-01-22 20:00:35 +00:00
  • b3639c4cc5 utils: fix docstring syntax. Catherine 2024-01-22 22:42:44 +00:00
  • db7e64960c lib.crc: make module documentation introduction consistent with other stdlib modules. Adam Greig 2024-01-18 00:17:40 +00:00
  • b40c18fb00 hdl.ast: suggest bit_select or word_select when indexing with Value. Wanda 2024-01-18 21:00:48 +01:00
  • 9e9790377a back.rtlil: fix emitting ROMs Wanda 2024-01-18 07:34:57 +01:00
  • 6211eca4ac docs: update cover, title, and copyright. Catherine 2024-01-17 17:49:50 +00:00
  • ae36b596bb hdl.mem: Switch to first-class IR representation for memories. Wanda 2024-01-16 21:19:03 +01:00
  • 2fecd1c78b examples.basic.pmux: Fix for RFC 39. Wanda 2024-01-16 13:09:16 +01:00
  • 95538a3e07 docs/lang: describe ResetInserter and EnableInserter. Catherine 2024-01-15 23:17:38 +00:00
  • be0e163279 docs/lang: clarify some text about clock domains. Catherine 2024-01-15 21:53:27 +00:00
  • b8ca2a09b4 docs: make the logo a bit smaller. Catherine 2024-01-15 19:58:35 +00:00
  • bf8faea51e hdl.ast: raise a sensible error for xxx in Value Wanda 2024-01-13 13:39:02 +01:00