whitequark c6150d0586 vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires. ... These only matter in simulation and after conversion to Verilog. During synthesis they cause Yosys to produce warnings: Warning: Wire $verilog_initial_trigger has an unprocessed 'init' attribute.		2020-11-06 01:31:14 +00:00
..
__init__.py	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00
intel.py	lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=.	2020-08-26 03:19:13 +00:00
lattice_ecp5.py	vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires.	2020-11-06 01:31:14 +00:00
lattice_ice40.py	vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires.	2020-11-06 01:31:14 +00:00
lattice_machxo2.py	sim: split into base, core, and engines.	2020-08-27 11:52:31 +00:00
lattice_machxo_2_3l.py	vendor.lattice_{ecp5,machxo_2_3l}: explain how to set up NMIGEN_ENV_Diamond on Windows.	2020-08-29 19:34:57 +00:00
quicklogic.py	vendor.quicklogic: part→package	2020-11-05 07:36:43 +00:00
xilinx_7series.py	vendor.xilinx_7series: byte swap generated bitstream	2020-11-03 09:39:49 +00:00
xilinx_spartan_3_6.py	lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=.	2020-08-26 03:19:13 +00:00
xilinx_ultrascale.py	vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate.	2020-08-26 15:45:58 +00:00