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Author SHA1 Message Date
Sebastian Holzapfel bf4f22d2d5 backends: s/ilang/rtlil as a result of https://github.com/YosysHQ/yosys/pull/4704 2025-08-18 17:46:28 +02:00
Wanda 3d2cd15435 sim: awaken all processes waiting on changed() at time 0. 2024-06-14 19:25:47 +00:00
Catherine 2c0265d827 Implement RFC 61: Minimal streams. 2024-06-14 18:51:38 +00:00
Wanda f5a8c07d54 sim: raise an exception on add_clock conflict with comb driver. 2024-06-14 17:47:08 +00:00
Catherine 6a2e789333 sim: forbid adding stimuli to a running simulation. 
Fixes #1368.
 2024-06-10 12:55:18 +00:00
Catherine c649045f35 lib.data: add a diagnostic for slicing data.View. 
This is meaningless for a view but meaningful for the underlying value.

Fixes #1375.
 2024-06-10 12:35:03 +00:00
Catherine 0140fe27e2 hdl._dsl: forbid empty string as submodule name. 
This is semantically ambiguous and breaks the RTLIL emitter.

Fixes #1209.
 2024-06-10 12:29:20 +00:00
Catherine 7870eb344b sim: document. 
This commit includes additional non-documentation changes, related to
issues found while documenting it:
- `Simulator.run_until()` no longer accepts a `run_passive=` argument.
  Passive no longer exist and in any case defaulting to `False` does not
  make a lot of sense from an API perspective.
- `add_clock()`'s `phase=` argument, when specified, no longer has
  `period/2` added to it. This wasn't the documented behavior in first
  place and it makes no sense to do that.
- `add_clock()` raises a `NameError` if a clock domain does not exist,
  instead of `ValueError`.
- `add_clock()` raises a `DriverConflict` if a clock domain is already
  being driven by a clock, instead of `ValueError`.
- GTKWave is no longer a part of the installation instructions, and both
  Surfer and GTKWave are recommended (in this order).
 2024-06-10 10:34:32 +00:00
Catherine e24b9b4983 tests: convert to async simulator syntax. 
This causes one test to fail due to a now-exposed bug.

Co-authored-by: Wanda <wanda-phi@users.noreply.github.com>
 2024-06-10 10:34:32 +00:00
Wanda 028d5d8073 hdl._ir, lib, vendor: add RequirePosedge, use it whenever required. 2024-05-29 15:49:31 +00:00
Wanda d3c312cf96 Implement RFC 55: New lib.io components. 2024-05-22 13:47:13 +00:00
Marek Materzok 51e0262710 sim: group signal traces according to their function. 2024-05-22 08:47:35 +00:00
Catherine 89eae72a41 sim: check type of testbench when adding one. 
Fixes #1363.
 2024-05-22 01:05:23 +00:00
Catherine 324c37f9fa docs/stdlib/io: document I/O buffer library. 2024-05-21 15:58:59 +00:00
Wanda 77dab7884c hdl._dsl: raise an error when modifying an already-elaborated Module. 
This renames the `FrozenMemory` exception to `AlreadyElaborated`
and reuses it for modules.

Fixes #1350.
 2024-05-18 00:59:00 +00:00
Jean-François Nguyen 496432edaa Implement RFC 30: Component metadata. 
Co-authored-by: Catherine <whitequark@whitequark.org>
 2024-05-10 13:17:24 +00:00
Wanda 1d2b9c309e back.rtlil: set read port init to all-x. 
This is an unfortunate necessity needed to fix memory inference regressions
introduced when we switched to using v2 cells. A better approach, compatible
with RFC 54, will need to be figured out for Amaranth 0.6.

Fixes #1011.
 2024-05-09 02:38:53 +00:00
Catherine 994fa81599 Implement RFC 36. 
This feature does not exactly follow the RFC because the RFC as written
is not implementable; the treatment of async resets in `tick()` triggers
had to be changed. In addition, iterating a trigger was made to watch
for missed events, in case the body of the `async for` awaited for too
long.

Co-authored-by: Wanda <wanda-phi@users.noreply.github.com>
 2024-05-06 11:09:46 +00:00
Catherine 5e59189c2b hdl: track domain renames in IR. 
Co-authored-by: Wanda <wanda@phinode.net>
 2024-05-06 11:09:46 +00:00
Wanda 9e82d54302 lib.io: make [io]_domain attributes always present. 
Having conditionally-present attributes causes more problems than it's
worth (see #1347). Just make them contain `None` when irrelevant.
 2024-05-05 04:57:52 +00:00
Wanda a7a7d32099 hdl._ast: deprecate Value.implies. 2024-04-16 19:26:08 +00:00
Wanda f243cea0fb sim: implement Format.* for memories in VCD. 2024-04-15 14:54:44 +00:00
Wanda 625dac376a hdl._dsl: improve error message on m.domains.cd_foo = .... 
Fixes #1331.
 2024-04-15 00:32:09 +00:00
Wanda 877a1062a6 hdl._nir: add combinational cycle detection. 
Fixes #704.
Fixes #1143.
 2024-04-13 14:01:47 +00:00
Wanda 8bf4f77616 sim: use Format.* for VCD output, remove hdl._repr. 
This also changes `decoder` a bit: when an enum is used as a decoder,
it is converted to a `Format.Enum` instead. The original enum is still
stored on the `decoder` attribute, so that it can be propagated
on `Signal.like`.
 2024-04-13 10:00:16 +00:00
Wanda 122be7849c sim: raise an error when overriding a combinationally-driven signal. 
Fixes #557.
 2024-04-13 09:40:41 +00:00
Wanda 16f187e7fa test_build_res: fix naming, squash warnings. 2024-04-13 08:38:38 +00:00
Wanda eebffc15d6 sim: add eval_format function. 
This will be used in an upcoming PR for VCD output.
 2024-04-12 20:14:11 +00:00
Wanda 580706fafd hdl._nir, back.rtlil: use Format.* to emit enum attributes and wires for fields. 2024-04-11 22:02:26 +00:00
Wanda 4cb2dde25f lib.data: add .format() implementation. 2024-04-11 19:02:06 +00:00
Wanda 67f5b61bcc hdl._ast: add enum name argument to Format.Enum. 
Turns out that RTLIL enum representation requires such, so add a place to store it.
 2024-04-11 18:45:16 +00:00
Wanda 1fdd9bf4e9 lib.enum: add .format() implementation. 2024-04-11 14:23:26 +00:00
Wanda 3c870d6b73 hdl._ast: add Format.Enum, Format.Struct, Format.Array. 2024-04-11 10:02:54 +00:00
Wanda 6f5d009fad sim: fix LRHS evaluation. 
Fixes #1269.
 2024-04-11 09:42:14 +00:00
Wanda 49a8a942e8 lib.enum: rename EnumMeta to EnumType. 
Fixes #1073.
 2024-04-11 08:40:12 +00:00
Wanda c59447c258 hdl._ast: make Signal.like work properly with ShapeCastables. 
Fixes #1285.
 2024-04-11 05:03:17 +00:00
Wanda 0be2dda656 lib.data: accept data.Const in *.const(). 2024-04-11 03:20:35 +00:00
Wanda cf534489a2 build.{plat,res}: post-lib.io cleanup. 2024-04-11 03:19:38 +00:00
Wanda 7fe62f810b Implement RFC 63: Remove amaranth.lib.coding 2024-04-11 00:15:55 +00:00
Catherine 1b81a47b69 test_lib_crc: speed up tests using multiprocessing. 2024-04-10 05:08:05 +00:00
Catherine 7dd93bea57 Document RFC 62. 
This includes a few minor code changes:
- Removing redundant `lib.memory.Memory.Init = hdl.MemoryData.Init`
  re-export;
- Renaming `FrozenError` to `FrozenMemory` and moving it to `.hdl`;
- Marking `ReadPort` and `WritePort` as `@final`.
 2024-04-09 15:52:34 +00:00
Wanda 7936b87667 hdl._ir: add caches for Matches and PriorityMatch cells. 2024-04-06 10:25:42 +00:00
Wanda 9bd536bbf9 hdl._ir: fix SwitchValue LHS lowering. 2024-04-04 23:13:00 +00:00
Catherine d94c97981a back.rtlil: implement remaining format specifiers. 
This requires a Yosys version from git. The requirement should be bumped
to a proper release before Amaranth 0.5.
 2024-04-04 03:03:09 +00:00
Wanda d3c5b958d3 back.rtlil: Opportunistically trim zero and sign extension on operands. 
Fixes #1148.
 2024-04-04 01:55:35 +00:00
Wanda 2d59242bf7 back.rtlil: refactor to use intermediate structures. 
Fixes #1100.
 2024-04-04 00:58:39 +00:00
Wanda 81c35a5922 hdl._ir: remove Fragment.drivers. 2024-04-04 00:55:06 +00:00
Wanda 262e24b564 hdl._ir: Remove uses of _[lr]hs_signals and _ioports. 2024-04-03 22:01:01 +00:00
Wanda 0e6d802de4 Implement RFC 58: Core support for ValueCastable formatting. 2024-04-03 19:59:19 +00:00
Wanda f21d3d0c6a hdl._ir: add all_undef_to_ff mode. 2024-04-03 18:47:45 +00:00