Commit graph

270 commits

Author SHA1 Message Date
whitequark 11914a1e67 hdl.ast: improve interaction of ValueCastable with custom __getattr__.
Avoid calling `__getattr__("_ValueCastable__lowered_to")` when
a ValueCastable has custom `__getattr__` implementation; this avoids
the need for downstream code to be aware of this implementataion
detail.
2021-10-03 20:28:07 +00:00
whitequark fac1b4b2d1 hdl.dsl: simplify. NFC. 2021-10-02 17:00:01 +00:00
whitequark e88d283ed3 hdl.ast: simplify Mux implementation. 2021-10-02 14:18:02 +00:00
Anton Blanchard 9f78ac0691
hdl.ast: remove quadratic time complexity in Statement.cast().
Using `sum(lst, [])` to flatten a list of lists has quadratic time
complexity. Use `chain.from_iterable()` instead. While not strictly
necessary to improve performance, convert to `map()`.

A test case writing out verilog for a 512k entry FIFO is 120x faster
with this applied.
2021-09-27 01:00:56 +00:00
Robin Ole Heinemann f570e1bbeb *: remove unused variables 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann 25caf4045b *: remove unused imports 2021-05-18 20:18:55 +00:00
Thomas Watson 7443f89200 hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements 2021-05-11 02:41:32 +00:00
whitequark c30dcea24d hdl.ast: handle int subclasses as slice start/stop values.
Fixes #601.
2021-03-18 23:52:23 +00:00
whitequark 7dde2aac7c hdl.ast: formatting. NFC. 2020-12-12 15:42:23 +00:00
whitequark 818c8bc464 hdl.ast: normalize case values to two's complement, not signed binary.
This was an especially insidious bug because the minus character is
valid in case values but has a completely different meaning (wildcard
rather than sign).

Fixes #559.
2020-12-12 12:42:12 +00:00
whitequark 39ff7203ba hdl.ast: remove dead code. NFC.
See #548.
2020-11-21 17:30:28 +00:00
awygle c1ed90807b
nmigen.hdl.rec: restore Record.shape().
This method was lost in commit abbebf8e.
2020-11-17 19:36:58 +00:00
awygle ea94c9cc45
hdl.rec: proxy operators correctly.
Commit abbebf8e used __getattr__ to proxy Value methods called on 
Record. However, that did not proxy operators like __add__ because
Python looks up the special operator methods directly on the class
and does not run __getattr__ if they are missing.

Instead of using __getattr__, explicitly enumerate and wrap every
Value method that should be proxied. This also ensures backwards
compatibility if more methods are added to Value later.

Fixes #533.
2020-11-09 20:20:25 +00:00
whitequark bde37fe2f2 hdl.ast: deprecate UserValue in favor of ValueCastable.
Closes #527.
2020-11-06 02:21:53 +00:00
awygle abbebf8efe
hdl.rec: migrate Record from UserValue to ValueCastable.
Closes #528.
2020-11-06 01:10:39 +00:00
awygle 06c734992f
hdl.ast: implement ValueCastable.
Closes RFC issue #355.
2020-11-06 00:20:54 +00:00
whitequark 9d62cbefa5 hdl.dsl: error on Elif immediately nested in an If.
I.e. on this code, which is currently not only wrongly accepted but
also results in completely unexpected RTL:

    with m.If(...):
        with m.Elif(...):
            ...

Fixes #500.
2020-10-22 13:23:06 +00:00
Xiretza eb152da59b hdl.ir: Update error message for Instance arguments
48d4ee4 added the option to specify attributes using Instance arguments,
but the error message wasn't updated accordingly.
2020-10-18 23:55:46 +00:00
Jean-François Nguyen 69ed4918b8 hdl.mem: document ReadPort and WritePort.
Fixes #496.
2020-09-17 15:47:46 +00:00
whitequark fde242aa47 hdl.ast: clarify exception message for out of bounds indexing.
Fixes #488.
2020-08-27 01:14:05 +00:00
whitequark 00026c6e4a hdl.ast: avoid unnecessary sign padding in ArrayProxy.
Before this commit, ArrayProxy would add sign padding (an extra bit)
a homogeneous array of signed values, or an array where all unsigned
values are smaller than the largest signed one. After this commit,
ArrayProxy would only add padding in arrays with mixed signedness
where all signed values are smaller or equal in size to the largest
unsigned value.

Fixes #476.

Co-authored-by: Pepijn de Vos <pepijndevos@gmail.com>
2020-08-26 07:07:48 +00:00
Adam Greig 07dc163105
hdl.mem: cast reset value for transparent read ports to integer. 2020-07-30 07:05:18 +00:00
awygle 659b0e8189
hdl.ast: don't inherit Shape from NamedTuple.
Fixes #421.
2020-07-07 05:17:03 +00:00
whitequark 399b8f9863 Add (heavily work in progress) documentation.
To render correctly, the docs require:
 * pygments/pygments#1441
2020-06-30 22:21:16 +00:00
Adam Greig 02e30b53cc
hdl.xfrm: preserve allow_reset_less when transforming ResetSignal.
Fixes #400.
2020-06-06 11:43:25 +00:00
Shawn Anastasio 2f7c3bf443
hdl.rec: preserve shapes when constructing a layout.
Preserve the original user-provided shape, while still checking 
its validity. This allows Enum decoders to work when specifying
record fields with Enums.

Fixes #393.
2020-06-05 03:19:46 +00:00
Robin Ole Heinemann 26a15b31f7 hdl.ast: fix typo 2020-05-24 16:56:15 +00:00
whitequark 7ea81f5f06 hdl.ast: add const-shift operations.
Also, clean up the rotate code a bit.

Fixes #378.
2020-05-20 03:18:33 +00:00
whitequark 72ef4303a9 hdl.ast: clarify docs for Value.rotate_{left,right}.
"Rotate modulo 2**len(self)" is redundant because that's just how
rotates work.
2020-05-19 23:43:25 +00:00
whitequark 404b2e07e4 hdl.dsl: check for unique domain name.
Fixes #385.
2020-05-19 23:40:49 +00:00
whitequark 35f3f7d630 hdl.ast: use SignalSet, not ValueSet, for _[lr]hs_signals().
The implementation of these functions likely predates support for
{Clock,Reset}Signal() in SignalKey.
2020-04-27 18:43:36 +00:00
awygle f2b4584b34
hdl.ir: typecheck convert(ports=) more carefully.
The `ports` argument to the `convert` functions is a frequent hotspot of
beginner issues. Check to make sure it is either a list or a tuple, and
give an appropriately helpful error message if not.

Fixes #362.
2020-04-24 21:15:00 +00:00
anuejn ff6c0327a7
hdl.rec: make Record inherit from UserValue.
Closes #354.
2020-04-16 16:46:55 +00:00
whitequark b4af217ed0 back.rtlil: translate enum decoders to Yosys enum attributes.
Fixes #254.
2020-04-15 14:45:59 +00:00
Dan Ravensloft 06c45c9ff0
hdl.ast: add Value.{rotate_left,rotate_right}. 2020-04-13 13:40:39 +00:00
whitequark 7a08901117 hdl.rec: improve repr() for Layout.
Fixes #326.
2020-04-12 04:47:40 +00:00
whitequark e9c75f7ca1 hdl.ast: improve repr() for Shape.
The default __repr__() from typing.NamedTuple does not include
the module name, so the replacement (which uses the preferred syntax
for specifying these shapes) doesn't either.
2020-04-12 03:59:56 +00:00
whitequark bb1bbcc51a hdl.mem: fix source location of ReadPort.en. 2020-04-05 02:00:06 +00:00
whitequark 2d1e12d00c hdl.ast: implement abs() on values. 2020-03-22 20:50:10 +00:00
awygle 4601dd0a69
Correctly handle resets in AsyncFIFO.
This commit improves handling of resets in AsyncFIFO in two ways:
  * First, resets no longer violate Gray counter CDC invariants.
  * Second, write domain reset now empties the entire FIFO.
2020-03-14 23:26:07 +00:00
awygle 2f8669cad6
lib.cdc: extract AsyncFFSynchronizer.
In some cases, it is necessary to synchronize a reset-like signal but
a new clock domain is not desirable. To address these cases, extract
the implementation of ResetSynchronizer into AsyncFFSynchronizer,
and replace ResetSynchronizer with a thin wrapper around it.
2020-03-08 21:37:40 +00:00
whitequark a14a5723c1 hdl.ast: fix off-by-1 in Initial.__init__(). 2020-02-19 01:28:14 +00:00
whitequark 27b47faf16 hdl.ast: add Value.{as_signed,as_unsigned}.
Before this commit, there was no way to do so besides creating and
assigning an intermediate signal, which could not be extracted into
a helper function due to Module statefulness.

Fixes #292.
2020-02-06 18:27:55 +00:00
whitequark a1c58633e6 hdl.dsl: make referencing undefined FSM states an error.
Before this commit, doing something like:

    with m.FSM():
        with m.State("FOO"):
            m.next = "bAR"
        with m.State("BAR"):
            m.next = "FOO"

would silently create an empty state `bAR` and get stuck in it until
the module is reset. This was done intentionally (in Migen, this code
would in fact miscompile), but in retrospect was clearly a bad idea;
it turns typos into bugs, while in the rare case that branching to
a completely empty state is desired, it is trivial to define one.

Fixes #315.
2020-02-06 17:47:46 +00:00
whitequark 97cc78a3db hdl.ir: type check ports.
Fixes #290.
2020-02-06 17:33:41 +00:00
whitequark 3df429703c hdl.dsl: reject name mismatch in m.domains.<name> +=.
This would violate invariants later in the elaboration process.

Fixes #282.
2020-02-06 16:13:59 +00:00
whitequark 86b57fe6b6 hdl.dsl: type check when adding to m.domains. 2020-02-06 15:19:16 +00:00
whitequark 31cd72c0b6 hdl.mem: add synthesis attribute support.
Fixes #291.
2020-02-06 14:53:16 +00:00
whitequark f7abe368a9 hdl.mem: document Memory. 2020-02-06 13:47:13 +00:00
whitequark dfcf7938ea hdl.{ast,dsl}: allow whitespace in bit patterns.
Fixes #316.
2020-02-04 07:54:54 +00:00