Commit graph

803 commits

Author SHA1 Message Date
whitequark 9749c70730 hdl.ir: lower domains before resolving hierarchy conflicts.
Otherwise, two subfragments with the same local clock domain would
not be able to drive its clock or reset signals. This can be easily
hit if using two ResetSynchronizers in one module.

Fixes #265.
2019-11-07 08:20:27 +00:00
whitequark e9887780af Improve .gitignore.
Fixes #264.
2019-11-02 02:03:14 +00:00
whitequark 4d6ad28f59 back.verilog: remove $verilog_initial_trigger after proc_prune.
$verilog_initial_trigger was introduced to work around Verilog
simulation semantics issues with `always @*` statements that only
have constants on RHS and in conditions. Unfortunately, it breaks
Verilator. Since the combination of proc_prune and proc_clean passes
eliminates all such statements, it can be simply removed when both
of these passes are available, currently on Yosys master. After
Yosys 0.10 is released, we can get rid of $verilog_initial_trigger
entirely.
2019-10-28 10:11:41 +00:00
whitequark 75d0fcd639 test: use #nmigen: magic comment instead of monkey patch.
Also, fix missing and incorrect src_loc_at arguments where
appropriate so the testsuite passes without warnings.
2019-10-26 06:37:08 +00:00
whitequark 9786d0c0e3 hdl.ir: allow disabling UnusedElaboratable warning in file scope.
This warning is usually quite handy, but is problematic in tests:
although it can be suppressed by using Fragment.get on elaboratable,
that is not always possible, in particular when writing tests for
exceptions raised by __init__, e.g.:

    def test_wrong_csr_bus(self):
        with self.assertRaisesRegex(ValueError, r"blah blah"):
            WishboneCSRBridge(csr_bus=object())

In theory, it should be possible to suppress warnings per-module
and even per-line using code such as:

    import re, warnings
    from nmigen.hdl.ir import UnusedElaboratable
    warnings.filterwarnings("ignore", category=UnusedElaboratable,
                            module=re.escape(__name__))

Unfortunately, not only is this code quite convoluted, but it also
does not actually work; we are using warnings.warn_explicit() because
we collect source locations on our own, but it requires the caller
to extract the __warningregistry__ dictionary from module globals,
or warning suppression would not work. Not only is this not feasible
in most diagnostic sites in nMigen, but also I never got it to work
anyway, even when passing all of module, registry, and module_globals
to warn_explicit().

Instead, use a magic comment at the start of a file to do this job,
which might not be elegant but is simple and practical. For now,
only UnusedElaboratable can be suppressed with it, but in future,
other linter parameters may become tweakable this way.
2019-10-26 06:17:14 +00:00
whitequark 8b05b28f5a back.rtlil: avoid exponential behavior when legalizing Part().
Fixes #259.
2019-10-26 02:01:53 +00:00
whitequark ffd10e3042 back.rtlil: fix lowering of Part() on LHS to account for stride. 2019-10-26 01:52:34 +00:00
whitequark 51269ad4a0 hdl.ast: simplify {bit,word}_select with constant offset.
We don't have any other convenient shortcut for x[off*w:(off+1)*w],
but using word_select to extract a single static range would result
in severe bloat of emitted code through expansion to dead branches.
Recognize and simplify this pattern.
2019-10-26 00:09:53 +00:00
whitequark 61e6267daf Explicitly restrict prelude imports.
It turns out that while Python does not import _private identifiers
when using * imports, it does nevertheless import all submodules.

Avoid polluting the namespace in the prelude by explicitly listing
all exported identifiers.
2019-10-21 10:39:21 +00:00
whitequark 9fba5ccb51 compat.fhdl.specials: fix argument parsing compatibility. 2019-10-17 07:54:36 +00:00
whitequark fb90043460 lib.io: use keyword-only arguments in Pin(). 2019-10-16 19:50:04 +00:00
whitequark 045f5e19a2 setup: fix commit 5198d99b. 2019-10-16 14:57:40 +00:00
Sebastien Bourdeauducq 07b3510218 verilog: fix yosys version error message 2019-10-16 13:10:19 +08:00
whitequark 58300d8eb6 back.verilog: fix Yosys version check. 2019-10-16 02:25:35 +00:00
whitequark 5198d99b5e setup: don't append local version for tags.
PyPI rejects any archives with local version.
2019-10-15 04:05:13 +00:00
whitequark 1bb3fa861c vendor.lattice_ice40: fix commit 88649def. 2019-10-14 15:55:11 +00:00
whitequark b3a8a43152 vendor.lattice_{ice40,ecp5}: fix typo. 2019-10-13 22:17:46 +00:00
whitequark 88649defda vendor.lattice_ice40: use pcf files instead of pre-pack Python scripts.
This allows to use nextpnr-ice40 built without Python with nMigen.
Requires nextpnr revision
YosysHQ/nextpnr@8c0610e84f or newer.
2019-10-13 21:56:40 +00:00
whitequark be6c16d0a2 build.plat: batch files use EQU, not EQ. 2019-10-13 21:45:56 +00:00
whitequark 2f9dab361f {,_}tools→{,_}utils
In context of nMigen, "tools" means "parts of toolchain", so it is
confusing to have a completely unrelated module also called "tools".
2019-10-13 18:53:38 +00:00
whitequark ccd28b40c2 vendor.lattice_{ice40,ecp5}: emit Verilog as well, for debugging. 2019-10-13 18:04:33 +00:00
whitequark b8b8e0ba0b build.plat: fold emit_prelude() into emit_commands().
Commit a783e464 broke all toolchains using bash.
2019-10-13 13:57:48 +00:00
Emily a783e4645d Refactor build script toolchain lookups.
Now environment variable overrides no longer infect the build scripts.

_toolchain.overrides is dropped as probably misguided in the first place.

Fixes #251.
2019-10-13 13:53:24 +00:00
whitequark 29253295ee hdl.ir: allow ClockSignal and ResetSignal in ports.
Fixes #248.
2019-10-13 03:39:56 +00:00
whitequark 722b3879f4 hdl.ir: cast instance port connections to Values.
Fixes #249.
2019-10-13 03:19:17 +00:00
whitequark 13650acbbc compat.fhdl.decorators: improve backwards compatibility. 2019-10-13 01:38:09 +00:00
whitequark d2c4c7c060 compat.fhdl.bitcontainer: update Value.wrap call. 2019-10-13 01:37:11 +00:00
whitequark 1334bd6a8b doc: bring COMPAT_SUMMARY up to date.
Fixes #112.
2019-10-12 23:15:09 +00:00
whitequark 1387e2f9df compat.genlib.fsm: add migration warning. 2019-10-12 22:48:08 +00:00
whitequark dbddddff17 compat.fhdl.decorators: add migration warnings. 2019-10-12 22:45:03 +00:00
whitequark a7e3b80409 hdl.ast: rename Slice.end back to Slice.stop.
It used to be called .stop in oMigen, and it's also called .stop in
Python range and slice objects, so keep that.
2019-10-12 22:40:48 +00:00
whitequark 77118fb9c9 compat.fhdl.structure: remove SPECIAL_* constants.
They cannot be used with nMigen designs since nMigen does not have
specials.
2019-10-12 22:40:48 +00:00
whitequark da48c05bdf _tools: extract most utility methods to a private package.
We don't want to guarantee backwards compatibility for most of them.
2019-10-12 22:40:48 +00:00
Jean-François Nguyen a97003d57a back.rtlil: fix DeprecationWarning. NFC. 2019-10-12 21:50:40 +00:00
whitequark b90687c988 Rename remaining wrap methods to cast.
Following commit d72d4a55.
2019-10-11 13:28:26 +00:00
whitequark a658cb2bbf hdl.ast: deprecate shapes like (1, True) in favor of signed(1).
This is a great improvement in clarity.
2019-10-11 13:22:08 +00:00
whitequark 706bfaf5e1 hdl.ast: deprecate Signal.{range,enum}.
Although constructor methods can improve clarity, there are many
contexts in which it is useful to use range() as a shape: notably
Layout, but also Const and AnyConst/AnyValue. Instead of duplicating
these constructor methods everywhere (which is not even easily
possible for Layout), use casting to Shape, introduced in 6aabdc0a.

Fixes #225.
2019-10-11 13:07:42 +00:00
whitequark 6aabdc0a73 hdl.ast: add an explicit Shape class, included in prelude.
Shapes have long been a part of nMigen, but represented using tuples.
This commit adds a Shape class (using namedtuple for backwards
compatibility), and accepts anything castable to Shape (including
enums, ranges, etc) anywhere a tuple was accepted previously.

In addition, `signed(n)` and `unsigned(n)` are added as aliases for
`Shape(n, signed=True)` and `Shape(n, signed=False)`, transforming
code such as `Signal((8, True))` to `Signal(signed(8))`.
These aliases are also included in prelude.

Preparation for #225.
2019-10-11 12:52:41 +00:00
whitequark db960e7c30 Consistently use {!r}, not '{!r}' in diagnostics.
This can cause confusion:
  * If the erroneous object is None, it is printed as 'None', which
    appears as a string (and could be the result of converting None
    to a string.)
  * If the erroneous object is a string, it is printed as ''<val>'',
    which is a rather strange combination of quotes.
2019-10-11 11:47:42 +00:00
whitequark fa1e466a65 hdl.ast: Operator.{op→operator}
Both "operator" and "operand" were shortened to "op" in different
places in code, which caused confusion.
2019-10-11 11:37:26 +00:00
whitequark 7ff4c6ce43 hdl.ast: simplify enum handling. 2019-10-11 11:16:00 +00:00
whitequark d72d4a55fd hdl.ast: Value.{wrap→cast}
Preparation for #225.
2019-10-11 10:49:34 +00:00
whitequark 9fe27a15ad vendor.xilinx_ultrascale: new supported family. 2019-10-10 16:35:48 +00:00
whitequark bfd4538df0 xilinx_7series: add grade platform property.
For some devices grade has to be omitted, so it is optional.
2019-10-10 16:33:00 +00:00
whitequark ef741594b5 vendor.lattice_machxo2: new supported family. 2019-10-10 16:22:29 +00:00
whitequark a7cc88f3d4 vendor: yosys is a required tool for all Verilog-based flows. 2019-10-10 14:38:09 +00:00
whitequark 730eff5d57 README: add device support matrix. 2019-10-10 00:50:16 +00:00
whitequark 8021e2dd76 vendor.intel: add Quartus support.
Co-authored-by: Dan Ravensloft <dan.ravensloft@gmail.com>
2019-10-10 00:35:13 +00:00
whitequark 7dfd7fb12a examples: update blinky, add some explanatory text about domains. 2019-10-09 23:19:28 +00:00
whitequark 7257c20a6a build.plat: elaborate result of create_missing_domain() against platform.
Before this commit, the result was elaborated without platform, which
caused generic implementation of e.g. ResetSynchronizer to be used.
2019-10-09 21:16:20 +00:00