whitequark
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3e59d857e1
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back.pysim: use bare ints for signal values (-5% runtime).
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2018-12-14 03:05:57 +00:00 |
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whitequark
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fb27c2520b
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back.pysim: new simulator backend (WIP).
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2018-12-13 18:02:46 +00:00 |
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whitequark
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71f1f717c4
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fhdl.cd: rename ClockDomain signals together with domain.
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2018-12-13 15:24:55 +00:00 |
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whitequark
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07c818e077
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fhdl.ir: move Fragment prepare logic from back.rtlil.
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2018-12-13 14:34:07 +00:00 |
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whitequark
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90f1503c91
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fhdl.ir: record port direction explicitly.
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
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2018-12-13 13:12:31 +00:00 |
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whitequark
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6251c95d4e
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compat.genlib.fsm: import/wrap Migen code.
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2018-12-13 12:41:19 +00:00 |
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whitequark
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9661e897e6
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fhdl.ir: a subfragment's input that we don't drive is also our input.
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2018-12-13 11:50:56 +00:00 |
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whitequark
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bb04c9e0da
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fhdl, back: trace and emit source locations of values.
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2018-12-13 11:44:06 +00:00 |
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whitequark
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b150f1915d
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fhdl.ir: don't crash propagataing ports in empty fragments.
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2018-12-13 11:25:49 +00:00 |
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whitequark
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72257b6935
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fhdl.ir: implement clock domain propagation.
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2018-12-13 11:01:03 +00:00 |
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whitequark
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fde2471963
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fhdl.ir: remove iter_domains().
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2018-12-13 10:18:57 +00:00 |
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whitequark
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f4340c19bb
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fhdl: cd_name→domain.
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2018-12-13 10:15:01 +00:00 |
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whitequark
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c5087edfa5
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fhdl.cd: add tests.
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2018-12-13 09:19:16 +00:00 |
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whitequark
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9bee90f1bd
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fhdl.xfrm: implement DomainRenamer.
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2018-12-13 08:57:14 +00:00 |
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whitequark
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19aa404628
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fhdl.xfrm: add tests for ResetInserter, CEInserter.
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2018-12-13 08:39:02 +00:00 |
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whitequark
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b1a89ef5fd
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fhdl.ir: add tests for port propagation.
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2018-12-13 08:09:39 +00:00 |
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whitequark
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d2e2d00e45
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fhdl.cd: rename ClockDomain.{reset→rst}.
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2018-12-13 07:27:27 +00:00 |
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whitequark
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e0a81edf4d
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fhdl.dsl: add tests for submodules.
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2018-12-13 07:24:28 +00:00 |
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whitequark
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932f1912a2
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fhdl.dsl: use less error-prone Switch/Case two-level syntax.
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2018-12-13 07:11:06 +00:00 |
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whitequark
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f70ae3bac5
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fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
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2018-12-13 06:06:51 +00:00 |
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whitequark
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5b8708017e
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fhdl.ast: fix Switch._?hs_signals() for switch without statements.
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2018-12-13 05:00:44 +00:00 |
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whitequark
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4df5c5de65
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fhdl.ir: explain how port enumeration works.
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2018-12-13 03:31:13 +00:00 |
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whitequark
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bfd0011aee
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fhdl.ir: make sure clocks and resets of used CDs appear as inputs.
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2018-12-13 02:43:22 +00:00 |
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whitequark
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22c76e5f90
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compat.fhdl.module: implement finalization.
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2018-12-13 02:36:15 +00:00 |
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whitequark
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f0f4c0ce61
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fhdl.ast: bits_sign→shape.
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2018-12-13 02:06:58 +00:00 |
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whitequark
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dc486ad8b9
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fhdl.ast: add tests for most logic.
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2018-12-13 02:06:55 +00:00 |
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whitequark
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b4dab74b2e
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compat.fhdl.{module,structure}: import/wrap Migen code (WIP).
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2018-12-12 15:47:34 +00:00 |
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whitequark
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1d4d00aac6
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fhdl.ast.Signal: implement .like().
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2018-12-12 14:43:19 +00:00 |
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whitequark
|
ad9b45adcd
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fhdl.ir: fix port threading code.
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2018-12-12 13:00:50 +00:00 |
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whitequark
|
0fac1f8d0f
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fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
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2018-12-12 12:38:24 +00:00 |
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whitequark
|
00f0b950f6
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fhdl.ast.Signal: fix typo.
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2018-12-12 12:37:30 +00:00 |
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whitequark
|
aab01d9e59
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fhdl.ast.Signal: implement attrs field.
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2018-12-12 11:30:40 +00:00 |
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whitequark
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4eadc1629a
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fhdl.ast.Signal: implement width derivation from min/max.
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2018-12-12 10:43:09 +00:00 |
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whitequark
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263d577323
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fhdl.ast.Signal: implement reset_less signals.
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2018-12-12 10:11:16 +00:00 |
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whitequark
|
1d46ffb591
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fhdl.ast.Signal: assign an internal name if tracer fails.
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2018-12-12 10:08:56 +00:00 |
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whitequark
|
6d5878a0ee
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fhdl.dsl: allow f.sync["dom"] as a synonym of f.sync.dom.
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2018-12-12 10:00:00 +00:00 |
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whitequark
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851ed06769
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ClockDomain.{rst→reset}, for consistency with ResetInserter.
nmigen.compat.ClockDomain would alias this, for Migen compatibility.
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2018-12-12 09:49:02 +00:00 |
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whitequark
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4d3258013d
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Initial commit.
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2018-12-12 03:18:44 +00:00 |
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