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47 commits

Author SHA1 Message Date
whitequark 2f9dab361f {,_}tools→{,_}utils 
In context of nMigen, "tools" means "parts of toolchain", so it is
confusing to have a completely unrelated module also called "tools".
 2019-10-13 18:53:38 +00:00
whitequark 29253295ee hdl.ir: allow ClockSignal and ResetSignal in ports. 
Fixes #248.
 2019-10-13 03:39:56 +00:00
whitequark 722b3879f4 hdl.ir: cast instance port connections to Values. 
Fixes #249.
 2019-10-13 03:19:17 +00:00
whitequark da48c05bdf _tools: extract most utility methods to a private package. 
We don't want to guarantee backwards compatibility for most of them.
 2019-10-12 22:40:48 +00:00
whitequark b90687c988 Rename remaining wrap methods to cast. 
Following commit d72d4a55.
 2019-10-11 13:28:26 +00:00
whitequark db960e7c30 Consistently use {!r}, not '{!r}' in diagnostics. 
This can cause confusion:
  * If the erroneous object is None, it is printed as 'None', which
    appears as a string (and could be the result of converting None
    to a string.)
  * If the erroneous object is a string, it is printed as ''<val>'',
    which is a rather strange combination of quotes.
 2019-10-11 11:47:42 +00:00
whitequark 7257c20a6a build.plat: elaborate result of create_missing_domain() against platform. 
Before this commit, the result was elaborated without platform, which
caused generic implementation of e.g. ResetSynchronizer to be used.
 2019-10-09 21:16:20 +00:00
whitequark 13316053e3 build.plat, hdl.ir: coordinate missing domain creation. 
Platform.prepare() was completely broken after addition of local
clock domains, and only really worked before by a series of
accidents because there was a circular dependency between creation
of missing domains, fragment preparation, and insertion of pin
subfragments.

This commit untangles the dependency by adding a separate public
method Fragment.create_missing_domains(), used in build.plat.

It also makes DomainCollector consider both used and defined domains,
such that it will work on fragments before domain propagation, since
create_missing_domains() can be called by user code before prepare().

The fragment driving missing clock domain is not flattened anymore,
because flattening does not work well combined with local domains.
 2019-08-19 22:52:01 +00:00
whitequark 003ba3b45f hdl.cd: implement local clock domains. 
Closes #175.
 2019-08-19 21:44:33 +00:00
whitequark 69d36dc139 hdl.xfrm: lower resets in DomainLowerer as well. 
Changed in preparation for introducing local clock domains.

Also makes elaboration about 15% faster.
 2019-08-19 21:44:30 +00:00
whitequark 404f99f022 hdl.xfrm: consider fragment's own domains in DomainLowerer. 
Changed in preparation for introducing local clock domains.
 2019-08-19 21:07:02 +00:00
whitequark e0b54b417e hdl.ir: allow adding more than one domain in missing domain callback. 
This is useful for injecting complex power-on reset logic.
 2019-08-03 18:19:40 +00:00
whitequark 9c28b61d9f hdl.ir: don't expose as ports missing domains added via elaboratables. 
The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.
 2019-08-03 16:39:21 +00:00
whitequark cea92e9531 hdl.ir: allow returning elaboratables from missing domain callback. 
This allows e.g. injecting a clock/reset generator in platform build
code on demand (i.e. if the domain is not instantiated manually).

See #57.
 2019-08-03 15:44:02 +00:00
whitequark fc846532c7 hdl.ir: raise DomainError if a domain is used but not defined. 
Before this commit, a KeyError would be raised elsewhere in guts of
hdl.ir, which is not helpful.
 2019-08-03 15:31:24 +00:00
whitequark fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing. 
See #57.
 2019-08-03 14:54:20 +00:00
whitequark 29fee01f86 hdl.ir: warn if .elaborate() returns None. 
Fixes #164.
 2019-08-03 12:30:39 +00:00
whitequark 2fa858b003 hdl.ir: make UnusedElaboratable a real warning. 
Before this commit, it was a print statement, and therefore, command
interpreter options like -Wignore did not affect it. There is no API
to access the warning filter list, so it was turned into a real
warning; and further, since Python 3.6, tracemalloc can be used
as a standard method to display traceback to allocation site instead
of the ad-hoc traceback logic that was used in Elaboratable before.
 2019-07-10 12:46:54 +00:00
whitequark 48d4ee4031 hdl.ir, back.rtlil: allow specifying attributes on instances. 
Fixes #107.
 2019-06-28 04:14:38 +00:00
whitequark 4379a5d6fe hdl.ir: rephrase elaboratable warning to not look like an error. 2019-06-04 13:11:15 +00:00
whitequark c6a0761b3a hdl.ir: accept LHS signals like slices as Instance io ports. 
This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)
 2019-06-03 02:39:14 +00:00
whitequark b64a31255c hdl.ir: accept expanded (kind, name, value) tuples in Instance. 
This is useful for e.g. programmatically generating parameters
without having to mess with kwargs dicts.
 2019-06-03 02:12:01 +00:00
whitequark b0ba960296 hdl.ir: silence unused elaboratable warning on interpreter crash. 2019-05-26 10:48:39 +00:00
whitequark 3392708e2b Consider Instances a part of containing fragment for use-def purposes. 
Fixes #70.
 2019-05-25 20:13:43 +00:00
whitequark c337246fc5 hdl.ir: when adding sync domain to a design, also add it to ports. 
Otherwise we end up in a situation where the examples don't have
clk and rst as ports, which is not nice.

Fixes #67.
 2019-05-15 06:44:50 +00:00
whitequark 39bc59c924 hdl.ir: during port propagation, defs should take priority over uses. 2019-05-13 15:34:13 +00:00
whitequark 958cb18b88 hdl.ir: only pull explicitly specified ports to toplevel, if any. 
Fixes #30.
 2019-05-12 05:21:23 +00:00
whitequark 585514e6ed hdl.ir: rework named port handling for Instances. 
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.

While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
 2019-04-22 07:46:47 +00:00
whitequark 44711b7d08 hdl.ir: detect elaboratables that are created but not used. 
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.

Fixes #3.
 2019-04-21 08:52:57 +00:00
whitequark 0a2a7025a6 hdl.xfrm: allow using FragmentTransformer on any elaboratable. 
Fixes #29.
 2019-04-10 00:23:11 +00:00
whitequark 49eef77c53 hdl: remove deprecated get_fragment() and lower() methods. 2019-04-09 23:53:43 +00:00
whitequark 8ee6bd80ff hdl.ir: raise a more descriptive error on non-elaboratable object. 2019-02-14 20:52:42 +00:00
whitequark 4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark 8c96675580 hdl.ast: add Past, Stable, Rose, Fell. 2019-01-17 04:31:27 +00:00
whitequark b534e92dd5 hdl.ir: allow explicitly requesting flattening. 2019-01-14 17:04:23 +00:00
whitequark 040811c2e5 hdl.ir: add an API for retrieving generated values, like FSM signal. 
This is useful for tests.
 2018-12-26 12:35:35 +00:00
whitequark 68dae9f50e hdl.ir: flatten hierarchy based on memory accesses, too. 2018-12-22 21:43:46 +00:00
whitequark fd89d2fc9d hdl.ir: factor out _merge_subfragment. NFC. 2018-12-22 19:04:49 +00:00
whitequark f6772759c8 hdl.ir: fix port propagation between siblings, in the other direction. 2018-12-22 00:31:31 +00:00
whitequark 913339c04a hdl.ir: fix port propagation between siblings. 2018-12-21 23:53:18 +00:00
whitequark fc7da1be2d hdl.ir: do not flatten instances or collect ports from their statements. 
This results in absurd behavior for memories.
 2018-12-21 13:52:18 +00:00
whitequark b0bd7bfaca hdl.ir: correctly handle named output and inout ports. 2018-12-21 04:03:03 +00:00
whitequark f7fec804ec ir: allow non-Signals in Instance ports. 2018-12-20 23:40:40 +00:00
whitequark c7f9386eab fhdl.ir: add black-box fragments, fragment parameters, and Instance. 2018-12-17 22:55:39 +00:00
whitequark 8d1639a5a8 hdl, back: add and use SignalSet/SignalDict. 2018-12-17 17:21:29 +00:00
whitequark 015998eba9 hdl.dsl: add clock domain support. 2018-12-16 23:51:24 +00:00
whitequark 790eb05a92 Rename fhdl→hdl, genlib→lib. 2018-12-15 14:25:31 +00:00
Renamed from nmigen/fhdl/ir.py (Browse further)