whitequark
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2566747061
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compat.fhdl.structure: fix Case().makedefault().
Fixes #100.
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2019-06-13 03:56:57 +00:00 |
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whitequark
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f689b777b4
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compat.fhdl.structure: always order default case as the very last.
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2019-06-13 03:56:57 +00:00 |
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whitequark
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537d91851d
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compat.fhdl.module: silence "unused elaboratable" warnings.
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2019-06-04 13:09:36 +00:00 |
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whitequark
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38917e4523
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compat.fhdl.specials: fix platform lowering for TSTriple again.
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2019-06-04 13:03:56 +00:00 |
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whitequark
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79a3710255
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compat.fhdl.specials: fix platform lowering.
get_tristate only has O/OE; the triple is created by get_input_output.
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2019-06-04 12:26:09 +00:00 |
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whitequark
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0cbb743df9
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compat.fhdl.module: implement some TODO'd deprecation warnings.
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2019-06-04 12:00:02 +00:00 |
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whitequark
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39ca0e6fa6
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compat.fhdl.module: CompatModule should be elaboratable.
Fixes #83.
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2019-06-04 11:11:31 +00:00 |
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whitequark
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4c443a7ef5
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compat.fhdl.specials: TSTriple is not an elaboratable.
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2019-06-03 09:39:38 +00:00 |
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Chris Osterwood
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699fe5a675
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Add import so that Tristate.elaborate builds
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2019-05-20 16:34:31 +00:00 |
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Alain Péteut
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c8e92c0612
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compat.fhdl.specials: fix Tristate, TSTriple.
* fix TSTriple instance.
* TSTriple, Tristate: tag as Elaboratable
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2019-04-22 09:57:12 +00:00 |
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Alain Péteut
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371dc8bebe
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compat.fhdl.specials: fix Tristate.
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2019-04-22 08:49:08 +00:00 |
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whitequark
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93d15abcf1
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compat.fhdl.specials: fix TSTriple.
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2019-04-22 08:15:03 +00:00 |
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whitequark
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287a0531b3
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lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin.
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2019-04-15 16:27:23 +00:00 |
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whitequark
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e844b0e095
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compat.fhdl.module: fix typo.
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2019-01-26 23:08:55 +00:00 |
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whitequark
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ce7ba70462
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compat.fhdl.specials: fix __all__ list.
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2019-01-26 22:59:33 +00:00 |
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whitequark
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7890c0adc8
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test.compat: reenable tests converting to Verilog.
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2019-01-26 15:29:09 +00:00 |
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whitequark
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4948162f33
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hdl.ir: rename .get_fragment() to .elaborate().
Closes #9.
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2019-01-26 02:31:12 +00:00 |
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whitequark
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e3b5b2acc8
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fhdl.specials: add compatibility shim for Tristate.
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2019-01-19 02:20:40 +00:00 |
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whitequark
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5361b4c22b
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compat: fix confusing naming for memory port address signal.
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2018-12-22 00:53:05 +00:00 |
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whitequark
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0df543b204
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compat: do not finalize native submodules twice.
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2018-12-22 00:02:31 +00:00 |
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whitequark
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00ef7a78d3
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compat: provide verilog.convert shim.
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2018-12-21 13:53:06 +00:00 |
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whitequark
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568d3c5b7d
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compat: provide Memory shim.
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2018-12-21 13:15:52 +00:00 |
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whitequark
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a90748303c
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compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.
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2018-12-18 20:03:32 +00:00 |
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whitequark
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015998eba9
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hdl.dsl: add clock domain support.
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2018-12-16 23:51:24 +00:00 |
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whitequark
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db5fd1e4c4
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compat.fhdl.structure: only convert to bool in If/Elif if necessary.
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2018-12-16 17:41:42 +00:00 |
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whitequark
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286a8009c8
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compat.fhdl: reexport Array.
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2018-12-16 10:39:54 +00:00 |
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whitequark
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790eb05a92
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Rename fhdl→hdl, genlib→lib.
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2018-12-15 14:25:31 +00:00 |
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whitequark
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9010805040
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compat.fhdl.structure: handle If/Elif with multi-bit condition.
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2018-12-15 00:10:54 +00:00 |
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whitequark
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ecea721f43
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compat.fhdl.module: allow adding native submodules to compat modules.
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2018-12-14 23:56:50 +00:00 |
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whitequark
|
1c7b43ea49
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Fix deprecations in Python 3.7.
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2018-12-14 23:56:50 +00:00 |
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whitequark
|
3bc3647380
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compat.fhdl.module: fix specials.
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2018-12-14 16:14:08 +00:00 |
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whitequark
|
3b23645fb7
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compat: add fhdl.specials.TSTriple shim.
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2018-12-14 16:09:51 +00:00 |
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whitequark
|
baba47251c
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compat.fhdl.module: update deprecation messages.
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2018-12-14 16:01:38 +00:00 |
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whitequark
|
6251c95d4e
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compat.genlib.fsm: import/wrap Migen code.
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2018-12-13 12:41:19 +00:00 |
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whitequark
|
f4340c19bb
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fhdl: cd_name→domain.
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2018-12-13 10:15:01 +00:00 |
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whitequark
|
22c76e5f90
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compat.fhdl.module: implement finalization.
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2018-12-13 02:36:15 +00:00 |
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whitequark
|
f0f4c0ce61
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fhdl.ast: bits_sign→shape.
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2018-12-13 02:06:58 +00:00 |
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whitequark
|
b4dab74b2e
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compat.fhdl.{module,structure}: import/wrap Migen code (WIP).
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2018-12-12 15:47:34 +00:00 |
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whitequark
|
356852a570
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compat.fhdl.bitcontainer: import/wrap Migen code.
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2018-12-12 15:22:34 +00:00 |
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