Commit graph

307 commits

Author SHA1 Message Date
Wanda 089213e19f Implement RFC 46: Change Shape.cast(range(1)) to unsigned(0). 2024-02-06 10:05:10 +00:00
Catherine 1fe7bd010f hdl: remove subclassing of AnyValue and Property.
This subclassing is unnecessary and makes downstream code more complex.
In the new IR, they are unified into cells with the same name anyway.
Even before that, this change simplifies things.
2024-02-05 05:58:12 +00:00
Wanda 115954b4d9 lib.fifo: add Memory as submodules instead of its ports. [NFC]
This makes the generated netlist very slightly nicer.
2024-01-31 21:14:08 +00:00
Catherine 357ffb680c hdl: remove Repl per RFC 10.
Closes #770.
2024-01-31 03:01:35 +00:00
Catherine 4da8adf7ba back.rtlil: remove _SyncBuilder. NFC
Amaranth doesn't emit sync rules for a while since these are private
for the Yosys Verilog frontend.
2024-01-31 02:47:52 +00:00
Catherine 572a60d838 hdl: add missing compatibility shims.
These were originally planned to be committed as a part of 5dd1223c,
but were lost during rebasing.
2024-01-31 02:05:17 +00:00
Wanda 1506f08b81 sim: use Value.cast on traces.
See kuznia-rdzeni/coreblocks#357.
2024-01-30 23:20:31 +00:00
Catherine ea3d6c9557 docs/reference: document compat guarantee, importing, shapes.
This commit also contains a related semantic change: it adds `Shape`
and `ShapeCastable` to the `__all__` list in `amaranth.hdl`. This is
consistent with the policy that is laid out in the new documentation,
which permits such additions without notice.

Co-authored-by: mcclure <mcclure@users.noreply.github.com>
2024-01-30 22:54:18 +00:00
Catherine 5dd1223cf8 amaranth.hdl: start all private names with an underscore.
This change completes commit 9dc0617e and makes all the tests pass.
It corresponds with the ongoing langauge reference documentation effort.

Fixes #781.
2024-01-30 17:20:45 +00:00
Catherine cf83193bf9 amaranth.hdl: rename internal modules to begin with an underscore.
This change completely breaks the library. It is done separately just
to make sure git tracks renames as such.
2024-01-30 17:20:45 +00:00
Catherine 8678d5fa14 hdl.dsl: warn if a case is defined after a default case. 2024-01-30 02:54:48 +00:00
Wanda e9299ccd0e hdl.ast: change warning on out-of-range reset to an error, improve it.
Fixes #1019.
2024-01-30 02:35:26 +00:00
Catherine 65d77f03fe back.verilog: forbid Yosys version range with dangling else bug.
Fixes #1049.
2024-01-24 16:45:22 +00:00
Catherine b3639c4cc5 utils: fix docstring syntax. 2024-01-22 23:25:14 +00:00
Adam Greig db7e64960c lib.crc: make module documentation introduction consistent with other stdlib modules. 2024-01-19 08:57:57 +00:00
Wanda b40c18fb00 hdl.ast: suggest bit_select or word_select when indexing with Value.
Fixes #1044.
2024-01-18 20:06:55 +00:00
Wanda 9e9790377a back.rtlil: fix emitting ROMs 2024-01-18 06:40:12 +00:00
Wanda ae36b596bb hdl.mem: Switch to first-class IR representation for memories.
Fixes #611.
2024-01-17 08:10:28 +00:00
Wanda bf8faea51e hdl.ast: raise a sensible error for xxx in Value 2024-01-14 00:36:44 +00:00
Wanda 86d14f584e Implement RFC 39: Change semantics of no-argument m.Case(). 2024-01-13 22:33:54 +00:00
Wanda eb1c55859e hdl.ir: collect source location for Instance. 2024-01-13 22:33:01 +00:00
Wanda 7f76914b74 Implement RFC 17: Remove log2_int.
Reexports of `amaranth.utils` functions are removed from
`amaranth._utils` to avoid a circular import issue (for `deprecated`).
Since this is a private module, this should not be a problem.
2024-01-11 04:45:17 +00:00
Wanda ea258fad71 Change uses of Case() to Default() in preparation for RFC 39. 2024-01-11 04:44:02 +00:00
Wanda 7e18786c97 hdl.ast: use operator.index instead of int.
This ensures things like `Const(1.5)` raise an error.

`int(operator.index())` is used since `operator.index(True)` on Python
3.9 and earlier returns `True` instead of `1`.
2024-01-10 18:07:48 +00:00
Wanda f25bf51a92 hdl.dsl: fix handling of redundant Case branches.
Fixes #1024.
2024-01-10 18:04:06 +00:00
Catherine 4e1b2451ec build.run: use correct working directory in BuildPlan.execute_local.
This regression was introduced in commit 3200a3961. Fixes #1020.
2024-01-09 15:55:54 +00:00
Catherine e59e2aa715 build.plat: add trailing newline at end of build script. 2024-01-09 15:55:54 +00:00
Jaro Habiger ded84fe9d6 sim: fix ValueCastable not being recognized as a coroutine command 2024-01-05 14:30:38 +00:00
Jaro Habiger c00e770f01 build.run: deprecate run_script argument in BuildPlan.execute_local() 2024-01-03 14:08:34 +00:00
Jaro Habiger b823a8ee9d build.run: add BuildPlan.execute_docker()
One usecase for this is using amaranth with vivado on macOs.
2024-01-03 14:08:34 +00:00
Jaro Habiger 3200a3961d build.run: factor out extract method 2024-01-03 14:08:34 +00:00
Jaro Habiger cc9fe89049 hdl.ast: fix Array not being indexable by ValueCastable 2024-01-03 13:46:16 +00:00
Catherine 5d9ad62f36 build.plat,vendor: start build.sh with #!/bin/sh.
The build scripts generated by Amaranth are designed to be invoked by
directly running them with any shell (some of them will re-invoke
themselves with `bash` specifically, when it's a toolchain requirement),
and they're not currently marked executable, so there's no shebang.

Add a shebang line to improve compatibility with cases where they are
treated as executables in their own right.
2024-01-03 11:45:57 +00:00
Wanda 0849e1af0b hdl.ast: make Slice const-castable.
Fixes #1006.
2023-12-30 11:28:03 +00:00
Wanda 6780c838b2 hdl.ast: fix Const.cast(Cat(...)) handling for signed numbers. 2023-12-30 11:27:08 +00:00
Wanda 8cd8cdde2b Implement RFC 20: Remove non-FWFT FIFOs.
Fixes #875.
2023-12-13 11:41:19 +00:00
Catherine 3ed78d98ea Implement RFC 18: Reorganize vendor platforms
Closes #873.
2023-12-13 11:24:37 +00:00
Catherine 9d4ffab104 compat: remove.
Fixes #692.
2023-12-13 11:20:12 +00:00
Catherine 750cbbc3c7 hdl: remove deprecated Sample, Past, Stable, Rose, Fell. 2023-12-13 11:13:14 +00:00
Catherine 475b0f35dd Implement RFC 19: Remove amaranth.lib.scheduler.
Closes #874.
2023-12-13 09:53:54 +00:00
Catherine 597b1b8839 Implement RFC 5: Remove Const.normalize.
Closes #754.
2023-12-13 09:53:54 +00:00
Catherine a2aa07cbc7 lib.wiring: document amaranth-lang/rfcs#2. WIP
Co-authored-by: Charlotte <charlotte@hrzn.ee>
2023-12-11 22:57:30 +00:00
Jean-François Nguyen d154bddf17 lib.wiring: preserve insertion order in SignatureMembers.__iter__. 2023-12-11 22:34:57 +00:00
Wanda 8e6ae9e6e0 Implement RFC 38: Component signature immutability.
Fixes #996.
2023-12-11 19:51:32 +00:00
Wanda 6ad0d21cc9 Implement RFC 37: Make `Signature` immutable.
Fixes #995.
2023-12-11 19:01:32 +00:00
Catherine b9c2404f22 lib.wiring: make values of In and Out be strings "In" and "Out".
Their `str()` and `repr()` values are already that; and the 0 and 1
don't make sense. The RFC leaves it unspecified.
2023-12-11 18:04:37 +00:00
Wanda e9545efb22 Implement RFC 35: Add ShapeLike, ValueLike. 2023-12-09 13:57:30 +00:00
Wanda 422ba9ea51 lib.wiring: use tracer to obtain default Signature path and src_loc.
Fixes #987.
2023-12-07 21:50:34 +00:00
Catherine 7db049f37f Remove remaining traces of $verilog_initial_trigger.
This construct was originally removed in commit b452e0e8. It has not been relevant since Yosys 0.10.
2023-12-07 21:10:11 +00:00
Catherine 120375dabe lib.wiring: fix __repr__ for PureInterface subclasses.
Fixes #988.
2023-12-05 04:46:11 +00:00
Wanda 0cdcab0fbb Implement RFC 34: Rename amaranth.lib.wiring.Interface to PureInterface. 2023-12-04 21:41:47 +00:00
Wanda ab6503e352 lib.wiring: add __repr__ to Interface. 2023-12-03 02:00:20 +00:00
Wanda 28139f5f4b sim: disambiguate duplicate names of traced signals
Fixes #976.
2023-12-03 00:51:35 +00:00
Catherine 193fdaccd0 lib.data: mark Field as @final. 2023-12-01 20:50:35 +00:00
Catherine 3597c48eee lib.data: improve FlexibleLayout documentation.
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
2023-12-01 20:50:35 +00:00
Wanda ef5cfa72bc Implement RFC 31: Enumeration type safety. 2023-11-29 10:50:34 +00:00
Catherine b0b193f1ad sim.pysim: admit non-signals in write_vcd(traces=...).
Rather than requiring each additional requested trace to be a signal,
all of the signals in the provided value are added to the GTKW file and
to the VCD file if they are not already there. This improves usability
for `lib.data` as struct fields can now be added to traces.
2023-11-28 12:21:21 +00:00
Wanda c6000b1097 lib.data: implement equality for View, reject all other operators. 2023-11-27 21:44:52 +00:00
Catherine 4bfe2cde6f sim: add support for dumping structure fields in VCD.
See #790.

This commit adds an entirely private API for describing formatting of
values that is used in the standard library, in departure from our
standing policy of not using private APIs in the standard library.

This is a temporary measure intended to get the version 0.4 released
faster, as it has been years in the making. It is expected that this
API will be made public in the version 0.5 after going through the usual
RFC process.

This commit only adds VCD lines for fields defined in `lib.data.Layout`
when using `sim.pysim`. The emitted RTLIL and Verilog remain the same.
It is expected that when `sim.cxxsim` lands, RTLIL/Verilog output will
include aliases for layout fields as well.

The value representation API also handles formatting of enumerations,
with no changes visible to the designer. The implementation of
`Signal(decoder=)` is changed as well to use the new API, with full
backwards compatibility and no public API changes.

Co-authored-by: Wanda <wanda@phinode.net>
2023-11-27 19:03:13 +00:00
Catherine 04f906965a lib.wiring: in is_compliant(sig, obj), check that obj is an interface object with that signature.
Fixes #935.
2023-11-27 18:50:41 +00:00
Catherine 8b48af6de8 lib.wiring: make sig.members += actually work. 2023-11-27 15:42:24 +00:00
Catherine 02756f6ec7 lib.wiring: comment cleanup. NFC 2023-11-27 15:42:24 +00:00
Catherine b2d8a18cbf lib.wiring: fix _gettypeattr fallback path. 2023-11-27 15:42:24 +00:00
Catherine a2e87b370e lib.wiring: fix typo in Signature.flatten. 2023-11-27 15:42:24 +00:00
Wanda 57748a66a6 lib.io: fix Pin.eq to work when FlippedInterface is involved.
This was broken by #915, when platform started handing out
`FlippedInterface` versions of `Pin`.
2023-11-27 06:35:55 +00:00
Catherine 74e613b49d lib.wiring: expand flipped object forwarding to respect @property and del.
Although `@property` is the most common case, any descriptors are now
properly supported.

The special casing of methods goes away as they work by having functions
implement the descriptor protocol. (`__get__` has some special behavior
to make this possible.)

This is some of the most cursed code I have ever written, yet it is
obviously necessary.
2023-11-26 12:53:59 +00:00
Catherine 79adbed313 sim.pysim: move name extractor functionality to Fragment.
At the moment there are two issues with assignment of names in pysim:
1. Names are not deduplicated. It is possible (and frequent) for names
   to be included twice in VCD output.
2. Names are different compared to what is emitted in RTLIL, Verilog,
   or CXXRTL output.

This commit fixes issue (1), and issue (2) will be fixed by the new IR.
2023-11-25 06:26:36 +00:00
Catherine e7b15e1321 sim._pyrtl: formatting. NFCI 2023-11-25 06:26:36 +00:00
William D. Jones abd74ead55 lib.wiring: flip sub-interfaces accessed via FlippedInterface. 2023-11-22 03:07:41 +00:00
Wanda 1802f7fddd lib.wiring: fix search-and-replace accident. NFC 2023-11-21 16:16:59 +00:00
Catherine fc06dd7644 back.verilog: require Yosys >=0.35.
Fixes #931.
2023-11-21 14:52:42 +00:00
Catherine f9da3c0d16 Pyupgrade to 3.8+. NFCI 2023-11-14 13:07:21 +00:00
Vegard Storheil Eriksen 879601380d ast: allow overriding Value operators. 2023-10-30 20:17:51 +00:00
Wanda 1c3227d956 lib.enum: use plain EnumMeta as metaclass when shape not used. 2023-10-25 17:00:24 +00:00
Wanda 4e4085a95b Implement RFC 20: Deprecate non-FWFT FIFOs.
Tracking issue #875.
2023-10-24 20:49:51 +00:00
Wanda a60b9960c5 lib.fifo: reimplement SyncFIFOBuffered without inner SyncFIFO. 2023-10-24 20:49:51 +00:00
Wanda bfd962670d lib.fifo: make fwft=True the default 2023-10-24 20:49:51 +00:00
Wanda 00699f7c41 lib.enum: allow using functional syntax for enum creation.
Fixes #910.
2023-10-21 05:46:12 +00:00
Catherine 7e254b8657 build.res: fix issue #937. 2023-10-20 15:08:10 +00:00
Wanda 1159e52921 tracer: recognize Python 3.13's CALL_KW opcode. 2023-10-20 14:45:11 +00:00
Nelson Gauthier bc316b41a8 lib.io: Pin.oe should have Flow.Out 2023-10-20 13:41:36 +00:00
Vegard Storheil Eriksen 392ead8d00 lib.data: return View from .const() 2023-10-10 09:59:37 +00:00
Wanda 470477a88f lib.wiring: fix Component.signature on subclasses without annotations.
On Python <3.10, classes without annotations do not get an
`__annotations__` member at all, so the `getattr` on a subclass falls
back to the parent class `__annotations__`, attempting to create
signature members twice.  Fix that by looking at the `__dict__` instead.
2023-10-08 22:49:47 +00:00
Jean-François Nguyen c7da6c1292 lib.wiring: add Interface to __all__. 2023-10-05 14:11:38 +00:00
Wanda ccf7aaf00d sim._pyrtl: fix masking for bitwise operands and muxes.
Fixes #926.
2023-10-05 12:26:47 +00:00
Catherine cce4e4462e build.plat: allow removing src attributes from RTLIL output.
This is important for Glasgow, which uses RTLIL hash as cache key,
and expects it to be stable between CI jobs.
2023-10-05 01:51:20 +00:00
Wanda c9416674d1 hdl.mem: fix transparent read handling for simple write ports.
Fixes #922.
2023-10-03 09:39:32 +00:00
Nelson Gauthier 8c56b2033f lib.wiring: Remove superfluous method alias 2023-09-27 17:50:33 +00:00
Catherine ec9da2d4d6 lib.wiring: Component.signature should not be a class method.
While the capability of providing signatures for components that are not
parametric is useful, most Amaranth gateware is heavily parameterized,
and the capability is not worth making most subclasses Liskov-incompatible
with the base class (where the derived class would not provide `signature`
as a class method anymore).
2023-09-27 11:32:06 +00:00
Catherine a90bc7b91a lib.wiring: create flipped interface from flipped signature.
Fixes #914.

Co-authored-by: Nelson Gauthier <nelson.gauthier@gmail.com>
2023-09-27 11:17:29 +00:00
Catherine fcafad1f70 hdl.ir: Elaboratable does not need ABCMeta as its metaclass.
This was introduced in commit 44711b7d, and was never used within
Amaranth itself. While technically a breaking change I think this
will not cause enough breakage to warrant a deprecation cycle
(nor can we make this a deprecation this without a lot of work).
2023-09-25 17:19:48 +00:00
Catherine 04b542a626 vendor._gowin: fix typo. 2023-09-25 14:15:11 +00:00
Catherine 57933b974d ast: fix pylance's type inference on Value._rhs_signals(). NFC 2023-09-25 14:15:11 +00:00
Catherine d27681b157 vendor.GowinPlatform: account for rouding error in frequency calculation. 2023-09-25 08:41:49 +00:00
Catherine 47851c2328 vendor.GowinPlatform: fix fencepost error in oscillator range.
Python ranges are half-open (exclusive).
2023-09-25 08:41:49 +00:00
Catherine bfd62569c8 vendor.GowinPlatform: improve oscillator frequency diagnostic. 2023-09-25 08:41:49 +00:00
Wanda 05cb82b8fc ast: fix const-castable expression handling in Signal(reset=).
The code to accept const-castable expressions was previously added in
0c4fda92fe, but it was untested and had
a few bugs.

Fixes #911.
2023-09-24 02:46:43 +00:00
crzwdjk 11d5bb19eb vendor._lattice_ice40: add an icepack_opts override
Add an icepack_opts override in case the user wants to pass
extra options to icepack as part of the build process.
2023-09-13 20:05:01 +00:00
Catherine ecba1a1863 back.rtlil: put hierarchy in module name instead of an attribute.
The attribute sees essentially no use and the information is much
better served by putting it in the module name. In addition this
means that the entire tree can be renamed simply by renaming the top
module.

Tools like GTKWave show the names of the instances, not the modules,
so they are not affected by the longer names.
2023-09-13 12:46:46 +00:00
Catherine a9d03805ff lib.io: add a deprecation warning on Pin.eq.
This will stop working once `Pin` is no longer inheriting from
`Record`.
2023-09-05 14:07:33 +00:00