Currently debug Verilog generation can take many 10's of seconds.
A new override can now be passed as `AMARANTH_debug_verilog`=0 on
the environment or by setting the `debug_verilog` keyword argument
to `Platform.build()` or `Platform.prepare_toolchain()` to `False`.
Fixes#623.
The existing functionality of get_override was poorly specified and
ill-purposed for boolean flags. This change extracts the core
variable retrieval logic to a helper function and adds a new handler
`get_override_flag` which special cases boolean flags.
The new behavior will also perform type checking on kwargs and inform
the user of the desired type expected.
Jinja2 version 2.11 has a broken dependency constraint that allows its
dependency on markupsafe to pull in a version that it is not actually
compatible with the interface of. Fix this by upgrading the dependency
to `~=3.0`. This requires a small patch to the code to replace the
deprecated `@jinja2.contextfunction` decorator with the replacement
`@jinja2.pass_context`since `@jinja2.contextfunction` is removed in
Jinja2 version 3.1.0.
Fix the strip_internal_attrs parameter to verilog.convert by passing it
down the call stack as intended.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Avoiding emission of sync processes in RTLIL allows us to avoid a dependency on
matching the behavior expected by Yosys, which generally expects sync processes
in RTLIL to match those emitted by the output from its own Verilog parser.
This also simplifies the logic used in emitting RTLIL overall.
Combinatorial processes are still emitted however. Without these the RTLIL does
not have a high-level understanding of Switch statements, which significantly
diminishes the quality of emitted Verilog, as these are converted to `$mux`
cells in Yosys, which become `?` constructs when converted back to Verilog.
Fixes#603.
Fixes#672.
Using floats to represent simulation time internally isn't ideal
instead use 1ps internal units while continuing to use a floating
point based interface for compatibility.
Fixes#535.
A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.
This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.
Fixes#588.
