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Author SHA1 Message Date
whitequark 8c30147e39 build.plat,vendor: allow clock constraints on arbitrary signals. 
Currently only done for Synopsys based toolchains (i.e. not nextpnr).

Refs #88.
 2019-09-11 23:35:43 +00:00
whitequark d1779bdb59 back: return name map from convert_fragment(). 2019-09-11 23:22:12 +00:00
whitequark 7342662bee hdl.ast: warn if reset value is truncated. 
Fixes #183.
 2019-09-10 07:26:34 +00:00
Darrell Harmon 27cedf4302 vendor.lattice_ecp5: pass ecppack_opts to ecppack. 2019-09-10 03:32:36 +00:00
whitequark 9b398b502e hdl.ast: check type of Sample(domain=...). 
Fixes #199.
 2019-09-08 23:55:05 +00:00
whitequark 3f6abc0b7a hdl.dsl: add Default(), an alias for Case() with no arguments. 
Fixes #197.
 2019-09-08 12:24:18 +00:00
whitequark eb04a2509e hdl.mem,lib,examples: use Signal.range(). 2019-09-08 12:19:13 +00:00
whitequark ccfbccc044 hdl.ast: add Signal.range(...), to replace Signal(min=..., max=...). 
Fixes #196.
 2019-09-08 12:10:31 +00:00
whitequark 5e9587bbbd Remove nmigen.lib from prelude. 
Currently it's just MultiReg, and there's no particularly good reason
to privilege this specific CDC primitive so much.
 2019-09-06 06:53:06 +00:00
whitequark 38831abdb4 Fix .gitignore. 2019-09-06 05:30:22 +00:00
whitequark 284b533995 setup: replace versioneer with setuptools_scm. 
Has the same problems with git-archive but is much less invasive.
 2019-09-06 05:20:42 +00:00
whitequark 943ce317af hdl.ast,back.rtlil: implement Cover. 
Fixes #194.
 2019-09-03 01:32:24 +00:00
whitequark 2e20622046 hdl.cd: add negedge clock domains. 
Fixes #185.
 2019-08-31 22:05:48 +00:00
Emily c4e8ac734f _toolchain,build.plat,vendor.*: add required_tools list and checks. 2019-08-31 00:05:47 +00:00
whitequark 4e91710933 vendor.lattice_ecp5: drive GSR synchronous to user clock by default. 
Fixes #167.
 2019-08-30 14:26:49 +00:00
whitequark a4b58cbf3a build.dsl: allow both str and int resource attributes. 2019-08-30 08:35:52 +00:00
Emily 98278a044d test.tools: use _toolchain.get_tool. 2019-08-28 11:52:16 +00:00
whitequark b14f5572d8 _toolchain: new module, for injecting dependencies in e.g. Nix. 2019-08-28 11:32:18 +00:00
whitequark 2168ff512b back.verilog: bump Yosys version requirement to 0.9. 
Fixes #55.
 2019-08-26 09:59:40 +00:00
whitequark b4b5d9e2ef vendor.lattice_ecp5: revert default toolchain to Trellis. 
This was unintentionally changed in 7fc1058e.
 2019-08-25 08:07:00 +00:00
whitequark 72cf4ca991 back.pysim: implement sim.add_clock(if_exists=True). 2019-08-23 08:53:48 +00:00
whitequark 906385c7f8 back.pysim: don't crash when trying to drive a nonexistent domain clock. 2019-08-23 08:37:59 +00:00
whitequark 9350620f89 build.run: add BuildPlan.digest(), useful for caching. 2019-08-23 01:10:51 +00:00
whitequark 7fc1058ed2 vendor.lattice_ecp5: add Diamond support. 2019-08-22 21:36:24 +00:00
whitequark c77274c1ad vendor: eliminate unnecessary LUT instantiation. 
Fixes #165.
 2019-08-22 21:29:20 +00:00
Reto Kramer b0ef53e095 examples/basic/uart: document divisor parameter. 2019-08-22 19:28:40 +00:00
whitequark 47bad3d20e back.rtlil: print real parameters with maximum precision. 2019-08-22 04:42:30 +00:00
Darrell Harmon aefde85031 back.rtlil: add support for real (float) parameters on Instances. 
Required for Xilinx MMCME2_BASE, etc.
 2019-08-22 04:13:05 +00:00
Darrell Harmon 6737ef79f9 vendor.xilinx_series7: use STARTUPE2, not STARTUPE3. 
STARTUPE3 is for Ultrascale.
 2019-08-21 22:25:55 +00:00
whitequark 5889e62668 vendor.lattice_ice40: remove --placer heap default option. 
It is not the place of nMigen to decide on this default, since both
SA and HeAP have valid uses that are not covered by the other.
 2019-08-21 21:32:38 +00:00
whitequark 531040d2fd vendor: style. NFC. 2019-08-21 21:32:36 +00:00
whitequark 25b280dba1 build.plat: remove TemplatedPlatform.unix_interpreter. 
Vendor toolchains generally require far more workarounds than this,
and we already have a perfectly fine way of overriding templates.
 2019-08-21 21:02:13 +00:00
whitequark 1fc63a62c0 back.pysim: allow coroutines as processes. 
This is a somewhat obscure use case, but it is possible to use async
functions with pysim by carefully using @asyncio.coroutine. That is,
async functions can call back into pysim if they are declared in
a specific way:

  @asyncio.coroutine
  def do_something(self, value):
    yield self.reg.eq(value)

which may then be called from elsewhere with:

  async def test_case(self):
    await do_something(0x1234)

This approach is unfortunately limited in that async functions
cannot yield directly. It should likely be improved by using async
generators, but supporting coroutines in pysim is unobtrustive and
allows existing code that made use of this feature in oMigen to work.
 2019-08-21 03:30:37 +00:00
William D. Jones c934fc66e9 test.test_examples: Convert pathlib-specific class to string. 
subprocess.check_call iterates over its arguments to check for spaces
and tabs, and on Windows, the pathlib-specific WindowsPath is not
iterable.
 2019-08-20 00:54:10 +00:00
whitequark 5ad409e897 back.verilog: parse output of yosys -V. 
See #55.
 2019-08-19 23:28:33 +00:00
whitequark 7ca29a5748 Fix nmigen.__version__ to work on git-archive artifacts. 
Fixes #137.
 2019-08-19 23:14:41 +00:00
whitequark 13316053e3 build.plat, hdl.ir: coordinate missing domain creation. 
Platform.prepare() was completely broken after addition of local
clock domains, and only really worked before by a series of
accidents because there was a circular dependency between creation
of missing domains, fragment preparation, and insertion of pin
subfragments.

This commit untangles the dependency by adding a separate public
method Fragment.create_missing_domains(), used in build.plat.

It also makes DomainCollector consider both used and defined domains,
such that it will work on fragments before domain propagation, since
create_missing_domains() can be called by user code before prepare().

The fragment driving missing clock domain is not flattened anymore,
because flattening does not work well combined with local domains.
 2019-08-19 22:52:01 +00:00
whitequark 77012fc143 vendor.lattice_ice40: use a local clock domain in create_missing_domain(). 2019-08-19 21:46:44 +00:00
whitequark a069d975b2 lib.cdc: use a local clock domain in ResetSynchronizer. 
This reverts commit 779f3ee906.
This reverts commit 300d47ca2e.
This reverts commit 9c54d0c061.
 2019-08-19 21:45:08 +00:00
whitequark 71ee64c403 README: fix typos. 2019-08-19 21:45:08 +00:00
whitequark 003ba3b45f hdl.cd: implement local clock domains. 
Closes #175.
 2019-08-19 21:44:33 +00:00
whitequark 9bdadbff09 back.pysim: index domains by identity, not by name. 
Changed in preparation for introducing local clock domains.
 2019-08-19 21:44:33 +00:00
whitequark 69d36dc139 hdl.xfrm: lower resets in DomainLowerer as well. 
Changed in preparation for introducing local clock domains.

Also makes elaboration about 15% faster.
 2019-08-19 21:44:30 +00:00
whitequark 404f99f022 hdl.xfrm: consider fragment's own domains in DomainLowerer. 
Changed in preparation for introducing local clock domains.
 2019-08-19 21:07:02 +00:00
whitequark 32bfbb11cb formal→asserts 
Closes #171.
 2019-08-19 20:23:24 +00:00
whitequark 2770db6de8 tracer: fix typo. 
Introduced in 62b3e366.
 2019-08-19 20:20:18 +00:00
whitequark ada1d6a603 build.plat: do not prepare fragments twice. 
Fixes #169.
 2019-08-19 19:49:51 +00:00
whitequark a2241fcfdb back.{rtlil,verilog}: split convert_fragment() off convert(). 
Because Fragment.prepare is not (currently) idempotent, it is useful
to be able to avoid calling it when converting. Even if it is made
idempotent, it can be slow on large designs, so it is advantageous
regardless of that.
 2019-08-19 19:49:51 +00:00
Robin Heinemann 8e048c5a7c build.dsl: add conn argument to Connector. 2019-08-18 19:56:25 +00:00
whitequark 84f2c3df2b compat.fhdl.decorators: avoid using deprecated NativeCEInserter. 2019-08-18 16:27:11 +00:00