usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity
961 commits 1 branch 0 tags 3.8 MiB
Commit graph

140 commits

Author SHA1 Message Date
whitequark 7aedb3e770 back.rtlil: lower maximum accepted wire size. 
In practice wires of just 100000 bits sometimes have unacceptable
performance with Yosys, so stick to Verilog's minimum limit of 65536
bits.
 2020-07-22 14:43:44 +00:00
whitequark d06add0aab back.rtlil: fix guard for division by zero. 
Oops... that should be checking the divisor, not the dividend. This
was discovered by running the test suite on cxxsim.
 2020-07-15 04:14:34 +00:00
whitequark fbf9e1f339 back.rtlil: handle signed and large Instance parameters correctly. 
Fixes #388.
 2020-05-19 23:33:14 +00:00
whitequark 6e29fbcc61 back.rtlil: fix incorrect escaping of signed parameters. 
Also, improve escaping code in general.
 2020-04-28 02:18:45 +00:00
anuejn ff6c0327a7
hdl.rec: make Record inherit from UserValue. 
Closes #354.
 2020-04-16 16:46:55 +00:00
whitequark b4af217ed0 back.rtlil: translate enum decoders to Yosys enum attributes. 
Fixes #254.
 2020-04-15 14:45:59 +00:00
whitequark ee73d39b8d back.rtlil: don't emit connections to zero width ports. 
Fixes #335.
 2020-04-13 17:04:13 +00:00
whitequark 792f35ac8f back.rtlil: refuse to create extremely large wires. 
Such wires are likely to trigger pathological behavior in Yosys and,
if applicable, other toolchains that consume Verilog converted from
RTLIL.

Fixes #341.
 2020-04-13 16:38:36 +00:00
whitequark 814ffde6fb back.rtlil: fix expansion of Part() for partial dummy writes. 
Before this commit, selecting a part that was fully out of bounds of
a value was correctly implemented as a write to a dummy wire, but
selecting a part that was only partially out of bounds resulted in
a crash.

Fixes #351.
 2020-04-13 15:56:39 +00:00
whitequark edd2bb2c49 back.rtlil: fix legalization of Part() with stride. 
Also known as word_select().
 2020-04-13 14:43:43 +00:00
whitequark b44870e779 Clarify a few comments. NFC. 2020-04-13 13:55:23 +00:00
whitequark 27b47faf16 hdl.ast: add Value.{as_signed,as_unsigned}. 
Before this commit, there was no way to do so besides creating and
assigning an intermediate signal, which could not be extracted into
a helper function due to Module statefulness.

Fixes #292.
 2020-02-06 18:27:55 +00:00
whitequark 31cd72c0b6 hdl.mem: add synthesis attribute support. 
Fixes #291.
 2020-02-06 14:53:16 +00:00
whitequark 3ac13eb8f9 back.rtlil: don't emit wires for empty signals. 
Fixes #312.
 2020-01-31 03:38:58 +00:00
whitequark 476ce15f04 back.rtlil: do not consider unreachable array elements when legalizing. 
Otherwise we produce invalid RTLIL.
 2020-01-01 15:26:05 +00:00
whitequark f8428ff505 back.rtlil: infer bit width for instance parameters. 
Otherwise, Yosys assumes it is always 32, which is often
inappropriate.
 2019-11-27 17:58:42 +00:00
whitequark 7c322e562a back.rtlil: extend shorter operand of a binop when matching sign. 
This is necessary because converting a large unsigned value to
a signed value of the same width may change its sign.

Fixes #271.
 2019-11-18 10:39:55 +00:00
whitequark 4d6ad28f59 back.verilog: remove $verilog_initial_trigger after proc_prune. 
$verilog_initial_trigger was introduced to work around Verilog
simulation semantics issues with `always @*` statements that only
have constants on RHS and in conditions. Unfortunately, it breaks
Verilator. Since the combination of proc_prune and proc_clean passes
eliminates all such statements, it can be simply removed when both
of these passes are available, currently on Yosys master. After
Yosys 0.10 is released, we can get rid of $verilog_initial_trigger
entirely.
 2019-10-28 10:11:41 +00:00
whitequark 8b05b28f5a back.rtlil: avoid exponential behavior when legalizing Part(). 
Fixes #259.
 2019-10-26 02:01:53 +00:00
whitequark ffd10e3042 back.rtlil: fix lowering of Part() on LHS to account for stride. 2019-10-26 01:52:34 +00:00
whitequark 2f9dab361f {,_}tools→{,_}utils 
In context of nMigen, "tools" means "parts of toolchain", so it is
confusing to have a completely unrelated module also called "tools".
 2019-10-13 18:53:38 +00:00
whitequark a7e3b80409 hdl.ast: rename Slice.end back to Slice.stop. 
It used to be called .stop in oMigen, and it's also called .stop in
Python range and slice objects, so keep that.
 2019-10-12 22:40:48 +00:00
whitequark da48c05bdf _tools: extract most utility methods to a private package. 
We don't want to guarantee backwards compatibility for most of them.
 2019-10-12 22:40:48 +00:00
Jean-François Nguyen a97003d57a back.rtlil: fix DeprecationWarning. NFC. 2019-10-12 21:50:40 +00:00
whitequark a658cb2bbf hdl.ast: deprecate shapes like (1, True) in favor of signed(1). 
This is a great improvement in clarity.
 2019-10-11 13:22:08 +00:00
whitequark fa1e466a65 hdl.ast: Operator.{op→operator} 
Both "operator" and "operand" were shortened to "op" in different
places in code, which caused confusion.
 2019-10-11 11:37:26 +00:00
whitequark 2512a9a12d back.rtlil: don't crash legalizing values with no branches. 
Fixes #239.
 2019-10-06 08:52:49 +00:00
whitequark 964c67453f back.rtlil: avoid unsoundness for division by zero. 
Fixes #238.
 2019-10-04 08:15:45 +00:00
whitequark d139f340b3 back.rtlil: don't cache wires for legalized switch tests. 
This causes miscompilation of code such as:

  r = Array([self.a, self.b])
  m = Module()
  with m.If(r[self.s]):
      m.d.comb += self.o.eq(1)
  return m
 2019-10-02 07:51:49 +00:00
whitequark d3f7cc8ed2 back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow} don't need to match. 2019-10-02 03:50:20 +00:00
whitequark 3a1dae591b back.rtlil: it is not necessary to match binop operand width. 2019-10-02 03:38:58 +00:00
whitequark 1621ceb65a hdl.ast: actually implement the // operator. 2019-09-28 19:33:24 +00:00
whitequark e3a1d05f23 back.rtlil: fix handling of certain nested arrays. 
This triggers on code like:

c1 = Signal()
c2 = Signal()
c3 = Signal()
v1 = Array([Const(1, 8), Const(2, 8)])[c1]
v2 = Array([Const(3, 8), Const(4, 8)])[c2]
v3 = Array([v1, v2])[c3]

Fixes #226.
 2019-09-24 18:32:26 +00:00
whitequark 7777b7b98c back.rtlil: give predictable names to anonymous subfragments. 
This is required for applying constraints to clocks in anonymous
subfragments in build.plat.
 2019-09-23 12:48:02 +00:00
whitequark 378e924280 hdl.ast: rename nbits to width. 
Also, replace `bits, sign = x.shape()` with more idiomatic
`width, signed = x.shape()`.

This unifies all properties corresponding to `len(x)` to `x.width`.
(Not all values have a `width` property.)

Fixes #210.
 2019-09-20 15:36:25 +00:00
whitequark b23a9794a4 hdl.ast: add Value.{any,all}, mapping to $reduce_{or,and}. 
Refs #147.
 2019-09-13 13:14:52 +00:00
whitequark d1779bdb59 back: return name map from convert_fragment(). 2019-09-11 23:22:12 +00:00
whitequark 943ce317af hdl.ast,back.rtlil: implement Cover. 
Fixes #194.
 2019-09-03 01:32:24 +00:00
whitequark 2e20622046 hdl.cd: add negedge clock domains. 
Fixes #185.
 2019-08-31 22:05:48 +00:00
whitequark 47bad3d20e back.rtlil: print real parameters with maximum precision. 2019-08-22 04:42:30 +00:00
Darrell Harmon aefde85031 back.rtlil: add support for real (float) parameters on Instances. 
Required for Xilinx MMCME2_BASE, etc.
 2019-08-22 04:13:05 +00:00
whitequark a2241fcfdb back.{rtlil,verilog}: split convert_fragment() off convert(). 
Because Fragment.prepare is not (currently) idempotent, it is useful
to be able to avoid calling it when converting. Even if it is made
idempotent, it can be slow on large designs, so it is advantageous
regardless of that.
 2019-08-19 19:49:51 +00:00
whitequark ed7e07c6c1 hdl.ast: implement Initial. 
This is the last remaining part for first-class formal support.
 2019-08-15 02:53:07 +00:00
whitequark 2e6627c4af back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS. 
Using 'x is legal RTLIL, in theory, but in practice it crashes Yosys
and when it doesn't, it causes Yosys to produce invalid Verilog.
Using a dummy wire is always safe and is not a major readability
issue as this is a rare corner case.

(It is not trivial to shorten the RHS in this case, because during
expansion of an ArrayProxy, match_shape() could be called in
a context far from the RHS handling logic.)
 2019-08-04 00:12:08 +00:00
whitequark d0ac8bf789 back.rtlil: actually match shape of left hand side. 
This comes up in code such as:
  Array([Signal(1), Signal(8)]).eq(Const(0, 8))
 2019-08-03 23:48:28 +00:00
whitequark ee03eab52f back.rtlil: fix sim-synth mismatch with assigns following switches. 
Closes #155.
 2019-08-03 13:27:47 +00:00
whitequark 94e13effad hdl.ast: deprecate Value.part, add Value.{bit,word}_select. 
Fixes #148.
 2019-08-03 13:07:06 +00:00
whitequark bcdc280a87 hdl.ast, back.rtlil: add source locations to anonymous wires. 
This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.

Also fixes incorrect source location on value.part().
 2019-08-03 12:51:57 +00:00
whitequark 37f363e338 back.rtlil: add decodings to cases when switching on a signal. 
Fixes #134.
 2019-07-09 19:48:15 +00:00
whitequark 00c5209a47 hdl.{ast,dsl},back.rtlil: track source locations for switch cases. 
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@93bc5aff.
 2019-07-09 19:26:47 +00:00