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146 commits

Author SHA1 Message Date
whitequark 99d205494a hdl.dsl: reword m.If(~True) warning to be more clear. 
Before this commit, it only suggested one thing (silencing it) and
that's wrong almost all of the time, so suggest the right thing
instead.
 2019-08-03 18:52:24 +00:00
whitequark e0b54b417e hdl.ir: allow adding more than one domain in missing domain callback. 
This is useful for injecting complex power-on reset logic.
 2019-08-03 18:19:40 +00:00
whitequark 9c28b61d9f hdl.ir: don't expose as ports missing domains added via elaboratables. 
The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.
 2019-08-03 16:39:21 +00:00
whitequark cea92e9531 hdl.ir: allow returning elaboratables from missing domain callback. 
This allows e.g. injecting a clock/reset generator in platform build
code on demand (i.e. if the domain is not instantiated manually).

See #57.
 2019-08-03 15:44:02 +00:00
whitequark fc846532c7 hdl.ir: raise DomainError if a domain is used but not defined. 
Before this commit, a KeyError would be raised elsewhere in guts of
hdl.ir, which is not helpful.
 2019-08-03 15:31:24 +00:00
whitequark fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing. 
See #57.
 2019-08-03 14:54:20 +00:00
whitequark ace2b5ff0a hdl.dsl: warn on suspicious statements like m.If(~True):. 
This pattern usually produces an extremely hard to notice bug that
will usually break a design when it is triggered, but will also be
hidden unless the pathological value of a boolean switch is used.

Fixes #159.
 2019-08-03 14:00:29 +00:00
whitequark 0a603b3844 hdl.ast: fix typo. 2019-08-03 13:21:09 +00:00
whitequark 94e13effad hdl.ast: deprecate Value.part, add Value.{bit,word}_select. 
Fixes #148.
 2019-08-03 13:07:06 +00:00
whitequark bcdc280a87 hdl.ast, back.rtlil: add source locations to anonymous wires. 
This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.

Also fixes incorrect source location on value.part().
 2019-08-03 12:51:57 +00:00
whitequark 29fee01f86 hdl.ir: warn if .elaborate() returns None. 
Fixes #164.
 2019-08-03 12:30:39 +00:00
whitequark 995e4adb8c hdl.xfrm: handle mem.{Read,Write}Port in CEInserter. 
Fixes #154.
 2019-07-31 05:20:05 +00:00
N. Engelhardt 698b005182 hdl.dsl: add getters to m.submodules. 2019-07-19 12:39:47 +00:00
whitequark 2fa858b003 hdl.ir: make UnusedElaboratable a real warning. 
Before this commit, it was a print statement, and therefore, command
interpreter options like -Wignore did not affect it. There is no API
to access the warning filter list, so it was turned into a real
warning; and further, since Python 3.6, tracemalloc can be used
as a standard method to display traceback to allocation site instead
of the ad-hoc traceback logic that was used in Elaboratable before.
 2019-07-10 12:46:54 +00:00
whitequark 00c5209a47 hdl.{ast,dsl},back.rtlil: track source locations for switch cases. 
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@93bc5aff.
 2019-07-09 19:26:47 +00:00
whitequark 0ab0a74ec1 hdl.rec: respect modifications to signals in Record.like(). 
Fixes #126.
 2019-07-08 10:59:15 +00:00
whitequark a7fbff94d8 hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain. 
Fixes #125.
 2019-07-08 10:26:49 +00:00
whitequark ec7fcd3697 hdl.xfrm: don't overwrite source locations on ClockDomain signals. 
On the sample of examples/basic/*.py, there are no remaining
incorrectly inferred locations.
 2019-07-08 09:58:12 +00:00
whitequark 8c9fdf907f hdl.{dsl,mem,xfrm}: inject appropriate source locations. 
This primarily fixes the problem with source location precision in
Module (which used to trace locations from __exit__ of the context
managers, by which point everything interesting has been lost), but
also improves memory port and control inserter source locations.

On the sample of examples/basic/*.py, the only incorrectly inferred
remaining location is clk pointing to hdl/mem.py:166.
 2019-07-08 09:58:12 +00:00
whitequark dac6275493 hdl.ast: use keyword-only arguments as appropriate. 
As a motivation/related refactor, make sure each AST node exposes
src_loc_at in the constructor.
 2019-07-08 09:58:12 +00:00
whitequark da1f58b7ae hdl.dsl: further clarify error message for incorrect nesting. 
Fixes #133.
 2019-07-07 01:03:59 +00:00
whitequark cb8be4a1b0 hdl.dsl: clarify error message for incorrect nesting. 
Refs #133.
 2019-07-07 00:59:57 +00:00
whitequark 3388b5b085 hdl.dsl: gracefully handle FSM with no states. 2019-07-07 00:59:34 +00:00
whitequark 2e4cc47fcb hdl.dsl: fix src_loc_at for FSM state signal. 2019-07-03 16:34:31 +00:00
whitequark 82903e493a back.rtlil: emit \src attributes for processes via Switch and Assign. 
The locations are unfortunately not very precise, but they provide
some improvement over status quo.
 2019-07-03 16:27:54 +00:00
whitequark e351e27206 hdl.ast: fix src_loc_at for Mux(). 2019-07-03 15:25:14 +00:00
whitequark 7059cb4931 hdl.rec: thread src_loc_at to all inner Signals and Records. 2019-07-03 14:49:20 +00:00
whitequark 5800f00776 hdl.rec: accept Record(src_loc_at=...). 2019-07-03 14:35:48 +00:00
whitequark 0ab215e5ed hdl.ast: recognize a Enum used as decoder and format it better. 2019-07-02 19:34:44 +00:00
whitequark 7cc0b8cbf0 hdl.mem: fix naming of registers inside unnamed memories. 
Before this commit, `None` would leak into the vcd file with pysim.
 2019-07-02 18:45:35 +00:00
whitequark 6b843b5be6 hdl.rec: implement slicing by component names. 
Fixes #121.
 2019-07-02 17:46:53 +00:00
whitequark 34f110100a hdl.rec: implement Record.like. 
Fixes #120.
 2019-07-02 17:46:53 +00:00
whitequark 94e8f479a5 hdl.mem: use read_port(domain="comb") for asynchronous read ports. 
This avoids the absurdity of the combination of arguments that is
read_port(domain="sync", synchronous=True).

Fixes #116.
 2019-07-01 19:56:49 +00:00
whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
 2019-06-28 04:37:08 +00:00
whitequark 48d4ee4031 hdl.ir, back.rtlil: allow specifying attributes on instances. 
Fixes #107.
 2019-06-28 04:14:38 +00:00
whitequark e5e23644a4 hdl.{ast,dst}: directly represent RTLIL default case. 
This makes RTLIL mildly nicer:

 casez ({ \$5 , \$3 , \$1  })
   3'bzz1:
       \$next\o  = \$7 ;
   3'bz1z:
       \$next\o  = \$9 ;
   3'b1zz:
       \$next\o  = \$11 ;
-  3'bz:
+  default:
       { \$next\co , \$next\o  } = \$13 ;
 endcase
 2019-06-25 22:01:14 +00:00
whitequark f1174655b1 hdl.ast: tighten assertion in Switch(). 2019-06-13 03:56:57 +00:00
whitequark e52b15d236 hdl.ast: add name_suffix=".." option to Signal.like(). 
This simplifies creation of related signals with nice names during
metaprogramming, e.g.

  def make_ff(m, sig):
      sig_ff = Signal.like(sig, name_suffix="_ff")
      m.d.sync += sig_ff.eq(sig)
      return sig_ff
 2019-06-12 22:26:57 +00:00
whitequark ad1a40c934 hdl.ast: implement values with custom lowering. 2019-06-11 07:01:44 +00:00
whitequark 58e39f90ce hdl.mem: coerce memory init values to integers. 
The coercion is carefully chosen to accept (other than normal ints)
instances of e.g. np.int64, but reject instances of e.g. float.
See https://stackoverflow.com/a/48940855/254415 for details.

Fixes #93.
 2019-06-11 03:38:44 +00:00
whitequark 4379a5d6fe hdl.ir: rephrase elaboratable warning to not look like an error. 2019-06-04 13:11:15 +00:00
whitequark 51c03ca391 hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}. 2019-06-04 10:26:01 +00:00
whitequark 9f643ce005 Clean up imports. 
This commit:
  * moves lists of universally useful imports from `nmigen` to
    `nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
  * replaces lots of imports from individual parts of `nmigen.hdl`
    with a star import from `nmigen.hdl`;
  * replaces imports in tests with what we expect downstream code
    to use;
  * adds some missing imports in `nmigen.formal`.
 2019-06-04 08:18:50 +00:00
whitequark a1940c5528 hdl.rec: unbreak hasattr(rec, ...). 
hasattr() requires that AttributeError be raised. Change __getitem__
to raise AttributeError, too, since it is fundamentally just sugar
for getattr().
 2019-06-03 07:43:31 +00:00
whitequark c6a0761b3a hdl.ir: accept LHS signals like slices as Instance io ports. 
This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)
 2019-06-03 02:39:14 +00:00
whitequark b8a61edc2f hdl.dsl: allow adding submodules with computed name, like with domains. 2019-06-03 02:22:55 +00:00
whitequark b64a31255c hdl.ir: accept expanded (kind, name, value) tuples in Instance. 
This is useful for e.g. programmatically generating parameters
without having to mess with kwargs dicts.
 2019-06-03 02:12:01 +00:00
whitequark b0ba960296 hdl.ir: silence unused elaboratable warning on interpreter crash. 2019-05-26 10:48:39 +00:00
whitequark 2b7dc37ffe hdl.rec: allow providing fields during construction. 
This allows creating records populated with e.g. signals with custom
names, or sub-records that are instances of Record subclasses.
 2019-05-25 22:06:56 +00:00
whitequark 3392708e2b Consider Instances a part of containing fragment for use-def purposes. 
Fixes #70.
 2019-05-25 20:13:43 +00:00