Commit graph

22 commits

Author SHA1 Message Date
Wanda 81c35a5922 hdl._ir: remove Fragment.drivers. 2024-04-04 00:55:06 +00:00
Wanda 606ebcd7a9 hdl._ast: Implement Mux in terms of SwitchValue.
Fixes #1075.
2024-04-03 11:00:58 +00:00
Wanda fc9369b8e1 hdl._xfrm: Simplify EnableInserter logic. 2024-03-03 18:38:20 +00:00
Wanda f8e2d26b8f hdl._ir: Inline AssignmentLegalizer into netlist building.
Fixes #1150.
2024-02-28 15:15:42 +00:00
Wanda 890e099ec3 Implement RFC 45: Move hdl.Memory to lib.Memory. 2024-02-19 22:24:58 +00:00
Wanda 6d65dc1366 hdl, back.rtlil: track and emit module/submodule locations. 2024-02-19 21:41:32 +00:00
Wanda 24a392887a Implement RFC 43: Rename reset= to init=. 2024-02-15 22:52:24 +00:00
Catherine 6f44438e58 hdl._ir,hdl._nir,back.rtlil: new intermediate representation.
The new intermediate representation will enable global analyses
on Amaranth code without lowering it to another representation
such as RTLIL.

This commit also changes the RTLIL builder to use the new IR.

Co-authored-by: Wanda <wanda@phinode.net>
2024-02-11 09:03:49 +00:00
Catherine 78981232d9 hdl.xfrm: add assignment legalizer.
Co-authored-by: Wanda <wanda@phinode.net>
2024-02-11 09:03:49 +00:00
Wanda 45dbce13df hdl: consistently use "comb" for combinatorial domain.
Fixes #1097.
2024-02-09 19:32:55 +00:00
Wanda b6c5294e50 hdl.MemoryInstance: refactor and add first-class simulation support. 2024-02-09 17:36:15 +00:00
Wanda 6e06fc013f hdl.ir: associate statements with domains.
Fixes #1079.
2024-02-09 05:33:16 +00:00
Catherine 5dd1223cf8 amaranth.hdl: start all private names with an underscore.
This change completes commit 9dc0617e and makes all the tests pass.
It corresponds with the ongoing langauge reference documentation effort.

Fixes #781.
2024-01-30 17:20:45 +00:00
Wanda ae36b596bb hdl.mem: Switch to first-class IR representation for memories.
Fixes #611.
2024-01-17 08:10:28 +00:00
Catherine 750cbbc3c7 hdl: remove deprecated Sample, Past, Stable, Rose, Fell. 2023-12-13 11:13:14 +00:00
Marcelina Kościelnicka 8c4a15ab92 hdl.mem: lower Memory directly to $mem_v2 RTLIL cell.
The design decision of using split memory ports in the internal
representation (copied from Yosys) was misguided and caused no end
of misery. Remove any uses of `$memrd`/`$memwr` and lower memories
directly to a combined memory cell, currently the RTLIL one.
2023-09-03 03:27:51 +00:00
Charlotte d218273b9b hdl.ast: deprecate Repl and remove from AST; add Value.replicate. 2023-06-22 03:52:55 +00:00
Catherine 0ee5de036c hdl.ast: deprecate Sample, Past, Rose, Fell, Stable.
See #526.
2023-02-28 14:30:04 +00:00
Catherine 5a79c351e3 Remove features deprecated in version 0.3. 2023-01-31 21:38:27 +00:00
whitequark 909a3b8be7 Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
whitequark bde37fe2f2 hdl.ast: deprecate UserValue in favor of ValueCastable.
Closes #527.
2020-11-06 02:21:53 +00:00
whitequark 67b957d4f4 tests: move out of the main package.
Compared to tests in the repository root, tests in the package have
many downsides:
  * Unless explicitly excluded in find_packages(), tests and their
    support code effectively become a part of public API.
    This, unfortunately, happened with FHDLTestCase, which was never
    intended for downstream use.
  * Even if explicitly excluded from the setuptools package, using
    an editable install, or setting PYTHONPATH still allows accessing
    the tests.
  * Having a sub-package that is present in the source tree but not
    exported (or, worse, exported only sometimes) is confusing.
  * The name `nmigen.test` cannot be used for anything else, such as
    testing utilities that *are* intended for downstream use.
2020-08-27 00:33:31 +00:00
Renamed from nmigen/test/test_hdl_xfrm.py (Browse further)