Commit graph

45 commits

Author SHA1 Message Date
whitequark
da4b810fe1 lib.fifo: adjust properties to have consistent naming. 2019-09-13 12:33:41 +00:00
whitequark
b92e967b78 lib.fifo: make fwft a keyword-only argument.
Because it accepts a boolean.
2019-09-12 19:38:18 +00:00
whitequark
1c091e67a4 lib.fifo: remove SyncFIFO.replace.
This obscure functionality was likely only ever used in old MiSoC
code, and doesn't justify the added complexity. It was also not
provided (and could not be reasonably provided) in SyncFIFOBuffered,
which made its utility extremely marginal.
2019-09-12 19:16:57 +00:00
whitequark
2d2ab6e09d lib.cdc: make domain properties private.
It is not correct to access domain properties from user code, because
it will not match the reality if DomainRenamer has been applied to
the module.
2019-09-12 13:54:48 +00:00
whitequark
73244f2bd2 lib.io: style. NFC. 2019-09-12 13:51:18 +00:00
whitequark
9893e3c044 lib.cdc: adjust ResetSynchronizer for new CDC primitive conventions.
Refs #97.
2019-09-12 13:48:45 +00:00
whitequark
8f659b6cd6 lib.cdc: adjust MultiReg for new CDC primitive conventions.
Refs #97.
2019-09-12 13:48:24 +00:00
whitequark
eb04a2509e hdl.mem,lib,examples: use Signal.range(). 2019-09-08 12:19:13 +00:00
whitequark
5e9587bbbd Remove nmigen.lib from prelude.
Currently it's just MultiReg, and there's no particularly good reason
to privilege this specific CDC primitive so much.
2019-09-06 06:53:06 +00:00
whitequark
a069d975b2 lib.cdc: use a local clock domain in ResetSynchronizer.
This reverts commit 779f3ee906.
This reverts commit 300d47ca2e.
This reverts commit 9c54d0c061.
2019-08-19 21:45:08 +00:00
whitequark
32bfbb11cb formal→asserts
Closes #171.
2019-08-19 20:23:24 +00:00
whitequark
ed7e07c6c1 hdl.ast: implement Initial.
This is the last remaining part for first-class formal support.
2019-08-15 02:53:07 +00:00
Alain Péteut
81e59832fb lib.fifo: fix typo. 2019-07-15 14:12:33 +00:00
Staf Verhaegen
ff343d5cf0 Pin: Add extra hierarchy level for name derivation 2019-07-14 19:30:12 +00:00
whitequark
94e8f479a5 hdl.mem: use read_port(domain="comb") for asynchronous read ports.
This avoids the absurdity of the combination of arguments that is
read_port(domain="sync", synchronous=True).

Fixes #116.
2019-07-01 19:56:49 +00:00
whitequark
779f3ee906 lib.cdc: avoid interior clock domains in ResetSynchronizer.
Such clock domains will "leak" into the enclosing scope, which is
generally undesirable. Also, this is instructive for a platform
overriding the behavior, since it provides guidance on how to
correctly instantiate platform-specific flops.

I've considered also doing this for MultiReg(), but it is very
challenging in presence of non-reset-less CDC FFs, since Yosys'
$dffsr primitive has separate set and clear inputs, and reshuffling
the reset value for those results in quite a bit of additional logic.

(That said, it might have to be done anyway, precisely because
letting Yosys generate this additional logic might prove too much
for the toolchain to cope with, and again, platform-independent
code should provide guidance to platform-specific code.)
2019-06-28 07:34:10 +00:00
whitequark
21379dd44b lib.cdc: eliminate no_retiming attributes.
See #115 for rationale.
2019-06-28 07:22:54 +00:00
Simon Kirkby
2423eabc15 lib.cdc: fix typo. 2019-06-09 10:24:01 +00:00
whitequark
9f643ce005 Clean up imports.
This commit:
  * moves lists of universally useful imports from `nmigen` to
    `nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
  * replaces lots of imports from individual parts of `nmigen.hdl`
    with a star import from `nmigen.hdl`;
  * replaces imports in tests with what we expect downstream code
    to use;
  * adds some missing imports in `nmigen.formal`.
2019-06-04 08:18:50 +00:00
whitequark
b42043f764 lib.io: add i_clk and o_clk to pin layout with xdr>=1. 2019-06-03 07:43:31 +00:00
whitequark
1eee7cd76f lib.io: allow dir="oe".
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.

E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
2019-06-03 04:28:53 +00:00
whitequark
c30617fc05 lib.io: allow Pin(xdr=0), representing a combinatorial I/O buffer. 2019-06-03 03:36:32 +00:00
Jean-François Nguyen
6a77122c2e lib.io: add a name argument to the Pin constructor. 2019-04-24 22:02:20 +00:00
whitequark
44711b7d08 hdl.ir: detect elaboratables that are created but not used.
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.

Fixes #3.
2019-04-21 08:52:57 +00:00
whitequark
287a0531b3 lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin. 2019-04-15 16:27:23 +00:00
Luke Wren
23a07b955f lib.cdc: add optional reset to MultiReg, and document its use cases. 2019-03-28 05:21:48 +00:00
whitequark
4027317835 lib.fifo: register GrayEncoder output before CDC.
Without this register, static hazards in the encoder could cause
multiple encoder output bits to toggle, which would be incorrectly
sampled by the 2FF synchronizer.

Reported by @Wren6991.
2019-03-03 18:23:51 +00:00
whitequark
f44ca291c1 lib.cdc: add ResetSynchronizer. 2019-01-26 18:07:59 +00:00
whitequark
4948162f33 hdl.ir: rename .get_fragment() to .elaborate().
Closes #9.
2019-01-26 02:31:12 +00:00
whitequark
7b25665fde back.pysim: fix behavior of initial cycle for sync processes.
The current behavior was introduced in 65702719, which was a wrong
fix for an issue that was actually fixed in 12e04e4e. This commit
effectively reverts 65702719 and 1782b841.
2019-01-25 20:37:56 +00:00
whitequark
1782b841b2 lib.fifo: in FIFOInterface.read(), check readable on the right cycle. 2019-01-22 07:03:46 +00:00
whitequark
2c80f35de4 lib.fifo: fix typo in AsyncFIFO documentation. 2019-01-22 05:47:50 +00:00
whitequark
e33580cf4c lib.fifo: add AsyncFIFO and AsyncFIFOBuffered. 2019-01-21 16:02:46 +00:00
whitequark
b6cff2c098 lib.coding: add GrayEncoder and GrayDecoder.
Unlike the Migen ones, these are purely combinatorial.
2019-01-20 02:20:34 +00:00
whitequark
9757157fe2 lib.coding: add width as attribute to all coders. 2019-01-20 01:59:09 +00:00
whitequark
3ed519383c lib.fifo: fix simulation read/write methods to take only one cycle. 2019-01-19 01:38:09 +00:00
whitequark
97b990272e lib.fifo: formally verify FIFO contract. 2019-01-19 00:52:56 +00:00
whitequark
5a831ce31c lib.fifo: add basic formal specification. 2019-01-17 05:40:25 +00:00
whitequark
b78a2be9f6 lib.fifo: port sync FIFO queues from Migen. 2019-01-16 17:20:38 +00:00
whitequark
c4276f7cf7 lib.io: pass pin to platform.get_tristate(). 2019-01-14 21:39:19 +00:00
whitequark
b534e92dd5 hdl.ir: allow explicitly requesting flattening. 2019-01-14 17:04:23 +00:00
whitequark
6f66885c09 lib.io: lower to platform-independent tristate buffer. 2019-01-14 16:50:04 +00:00
whitequark
3ea35b8566 lib.coding: fix tests to actually run, and fix code to fix tests. 2018-12-27 21:45:55 +00:00
whitequark
528747703d lib.coding: port from Migen. 2018-12-26 13:19:34 +00:00
whitequark
790eb05a92 Rename fhdl→hdl, genlib→lib. 2018-12-15 14:25:31 +00:00