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• ebbdac9798
  vendor.intel: add support for Cyclone V internal oscillator Konrad Beckmann 2020-11-06 12:35:18 +0100
• bde37fe2f2 hdl.ast: deprecate UserValue in favor of ValueCastable. whitequark 2020-11-06 02:21:53 +0000
• c9fd000103 sim.pysim: avoid redundant VCD updates. whitequark 2020-11-06 02:05:35 +0000
• 6e7dbe004e examples: clean up oudated code. whitequark 2020-11-06 01:52:00 +0000
• bb6a233626 Fix commit 8313d6e7. whitequark 2020-11-06 01:54:25 +0000
• 8313d6e71c cli: update deprecated import. whitequark 2020-11-06 01:39:04 +0000
• db5a981f43 CI: add CPython 3.9 to test matrix. whitequark 2020-11-06 01:41:35 +0000
• 10fd5cff4b CI: run testsuite with -Werror. whitequark 2020-11-06 01:38:03 +0000
• c6150d0586 vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires. whitequark 2020-11-06 01:31:14 +0000
• abbebf8efe
  hdl.rec: migrate Record from UserValue to ValueCastable. awygle 2020-11-05 17:10:39 -0800
• 06c734992f
  hdl.ast: implement ValueCastable. awygle 2020-11-05 16:20:54 -0800
• 0ef01b1282 vendor.quicklogic: part→package whitequark 2020-11-05 07:36:13 +0000
• 14a5c42a8b vendor.xilinx_7series: byte swap generated bitstream Norbert Braun 2020-11-02 22:00:17 +0100
• b15f0562a6 lib.fifo: fix {r,w}_level in AsyncFIFOBuffered Jaro Habiger 2020-08-18 13:11:30 +0200
• c7014f84ea lib.fifo: fix level on fifo full Jaro Habiger 2020-11-03 10:10:07 +0100
• 781a3aa767
  vendor.lattice_ice40: zero-pad CLKHF_DIV in SB_HFOSC instance. David Lattimore 2020-11-02 17:19:47 +1100
• 8fe319f065 vendor.quicklogic: utilize internal SoC clock in EOS-S3 Jan Kowalewski 2020-10-21 14:24:41 +0200
• b88009bd96 vendor.quicklogic: fix toolchain nomenclature Jan Kowalewski 2020-10-20 12:46:58 +0200
• 05decc43b2 lib.fifo.AsyncFFSynchronizer: check input and output signal width Robin Ole Heinemann 2020-10-28 00:41:01 +0100
• 765c15c709
  setup: link to latest docs if VCS information is not available. Ben Newhouse 2020-10-27 01:16:25 +0000
• e3207b74f4 build.dsl: clean up inversion logic. whitequark 2020-10-26 19:50:21 +0000
• 87454b0b6f back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion. whitequark 2020-10-25 01:59:46 +0000
• 5581fdc1e8 CI: disable codecov project status. whitequark 2020-10-25 00:13:39 +0000
• d8273a15c3
  lib.fifo.AsyncFIFO: fix incorrect latency of r_level. anuejn 2020-10-24 16:58:23 +0200
• ca6fa036f6
  tests: make spec directory name unique per test method. anuejn 2020-10-22 23:38:44 +0200
• df70aae887 sim._pyrtl: sign extend RHS of assignment. whitequark 2020-10-22 16:08:38 +0000
• 9d62cbefa5 hdl.dsl: error on Elif immediately nested in an If. whitequark 2020-10-22 13:23:06 +0000
• 2c505deacc vendor.quicklogic: fix syntax Jan Kowalewski 2020-10-19 12:09:50 +0200
• 12327aedf8 setup.py: Exclude "tests" package Xiretza 2020-10-19 19:23:43 +0200
• eb152da59b hdl.ir: Update error message for Instance arguments Xiretza 2020-10-16 18:36:56 +0200
• a6db99b05e README: Quicklogic EOS S3 is now supported. whitequark 2020-10-15 18:10:39 +0000
• 80194e1a7e CI: fix code coverage collection. whitequark 2020-10-15 18:09:04 +0000
• 9746138e55
  vendor.quicklogic: new platform. Jan Kowalewski 2020-10-15 20:02:25 +0200
• e58233b441 tests: keep comments up to date. NFC. whitequark 2020-10-15 17:02:50 +0000
• d22b2c5604 build.plat: avoid type confusion in _check_feature. whitequark 2020-10-15 08:54:48 +0000
• 69ed4918b8 hdl.mem: document ReadPort and WritePort. Jean-François Nguyen 2020-09-15 02:20:35 +0200
• 47ecc16283
  vendor.lattice_{ecp5,machxo_2_3l}: explain how to set up NMIGEN_ENV_Diamond on Windows. William D. Jones 2020-08-29 15:34:57 -0400
• d12c7827a0 setup: synchronize builtin-yosys dependency. whitequark 2020-08-27 13:39:42 +0000
• 955f3f6dcc back.verilog: use proc -nomux if it is available. whitequark 2020-08-27 13:03:15 +0000
• b65e11f38f sim: split into base, core, and engines. whitequark 2020-08-27 10:17:02 +0000
• 9bdb7accc8 sim.pysim: in write_vcd(), close files if an exception is raised. whitequark 2020-08-27 08:33:48 +0000
• 9bc42cb8c5 sim._pyclock: new type of process. whitequark 2020-08-27 07:54:27 +0000
• c00219d9f3 sim._pycoro: make src_loc() more robust. whitequark 2020-08-27 07:11:14 +0000
• 141eaf0e40 _toolchain.cxx: work around PyPy missing LDCXXSHARED sysconfig variable. whitequark 2020-08-27 06:53:14 +0000
• 4180cc537b _toolchain.cxx: new toolchain. whitequark 2020-08-27 06:24:18 +0000
• fde242aa47 hdl.ast: clarify exception message for out of bounds indexing. whitequark 2020-08-27 01:14:05 +0000
• 5b01499901 nmigen.test.utils: restore FHDLTestCase to gracefully deprecate it. whitequark 2020-08-27 00:46:50 +0000
• 67b957d4f4 tests: move out of the main package. whitequark 2020-08-27 00:33:31 +0000
• ef7a3bcfb1
  build.run: implement SSH remote builds using Paramiko. William D. Jones 2020-08-26 18:49:49 -0400
• 07a3685da8 back.rtlil: do not squash empty modules. whitequark 2020-08-26 22:45:19 +0000
• 12beda6e5b back.verilog: omit Verilog initial trigger only if Yosys adds it. whitequark 2020-08-26 09:01:57 +0000
• 6d9852506f vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate. whitequark 2020-08-26 10:18:02 +0000
• abaa9091f4 vendor.xilinx_7series: unbreak. whitequark 2020-08-26 14:57:31 +0000
• 8c6c3643cd sim._pyrtl: optimize uses of reflexive operators. whitequark 2020-08-26 13:26:38 +0000
• 38b75ba4bc back.cxxrtl: actualize Yosys version requirement. whitequark 2020-08-26 09:16:46 +0000
• 00026c6e4a hdl.ast: avoid unnecessary sign padding in ArrayProxy. whitequark 2020-08-26 06:58:22 +0000
• cb81618c28 sim._pyrtl: fix miscompilation of -(Const(0b11, 2).as_signed()). whitequark 2020-08-26 04:15:26 +0000
• 0802f943ba lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=. whitequark 2020-08-26 03:19:13 +0000
• 630c0fd99a vendor.lattice_machxo_2_3l: add SRAM svf generation Robin Ole Heinemann 2020-08-04 17:30:18 +0200
• 4e208b0ac1 vendor: Add initial support for Symbiflow for Xilinx 7-series Mariusz Glebocki 2020-08-02 18:48:26 +0200
• 77616837e8 vendor.xilinx_7series: add _part property getter Mariusz Glebocki 2020-08-24 13:03:59 +0200
• 15f150337f cli: Improve help texts Xiretza 2020-08-22 15:46:58 +0200
• e46118dac0 docs/lang: use less confusing placeholder variable names. whitequark 2020-08-15 13:00:50 +0000
• 73f672f57c
  lib.fifo: add r_level and w_level to all FIFOs awygle 2020-08-15 01:40:56 -0700
• f6f9d68f24 Add Linguist tags to .gitattributes. whitequark 2020-08-13 03:10:17 +0000
• b86acdc601 vendor.lattice_{ecp5,machxo_2_3l}: specify impl-dir correctly Robin Ole Heinemann 2020-08-10 17:23:29 +0200
• d964ba9cc4 build,vendor: never carry around parts of differential signals. whitequark 2020-07-31 13:17:39 +0000
• c9662c5ff8 vendor.xilinx_{7series,ultrascale}: use BUFGCTRL rather than BUFGCE. whitequark 2020-07-31 14:45:38 +0000
• 07dc163105
  hdl.mem: cast reset value for transparent read ports to integer. Adam Greig 2020-07-30 08:05:18 +0100
• 20f9ab9d7a
  nmigen.lib.scheduler: add RoundRobin. Jean THOMAS 2020-07-28 23:02:01 +0200
• 8117ef6692
  tests: fix remove unnecessary workaround for some unittest assertions. Jacob Graves 2020-07-28 13:35:25 -0600
• c75fa45fd8 vendor.xilinx_{7series,ultrascale}: add SIM_DEVICE parameter. whitequark 2020-07-22 02:13:10 +0000
• f7a8fcc94c
  vendor.lattice_ecp5: add missing differential IO types. Jean THOMAS 2020-07-23 14:24:31 +0200
• 7aedb3e770 back.rtlil: lower maximum accepted wire size. whitequark 2020-07-22 14:43:44 +0000
• 1321c4591d sim._pycoro: avoid spurious wakeups. whitequark 2020-07-22 14:32:45 +0000
• d71e19e27c CI: replace Travis with GitHub Actions. whitequark 2020-07-22 08:11:59 +0000
• 0899ff366b compat.fhdl.bitcontainer: fix value_bits_sign(). whitequark 2020-07-21 02:53:29 +0000
• 5ccc2122ce CI: use WASM yosys instead of building our own. whitequark 2020-07-16 08:00:10 +0000
• d06add0aab back.rtlil: fix guard for division by zero. whitequark 2020-07-15 04:09:58 +0000
• d714d78de1 docs: add install instructions for arch Filipe Laíns 2020-07-14 00:42:02 +0100
• 127fce8f48 CI: run on pull requests as well, not just pushes. whitequark 2020-07-14 00:25:11 +0000
• ecb3a69d48 lib.cdc: fix typo. whitequark 2020-07-13 23:16:27 +0000
• 58f1d4bcb6
  sim.pysim: write the next, not curr signal value to the VCD file Jacob Lifshay 2020-07-12 19:10:01 -0700
• 0a90aa1b17 sim.pysim: use VCD aliases to reduce space and time overhead. whitequark 2020-07-11 12:25:31 +0000
• 30e2f91176 sim: simplify. NFC. whitequark 2020-07-08 17:30:06 +0000
• d7a87fef42 back.pysim→sim.pysim; split into more manageable parts. whitequark 2020-07-08 12:49:38 +0000
• 23da2fdda6 vendor.xilinx_{7series,ultrascale}: remove grade property. whitequark 2020-07-08 09:08:00 +0000
• 6d417568ad back.pysim: only extract signal names if VCD is requested. whitequark 2020-07-08 08:29:20 +0000
• 3c3cfd48fb back.pysim: reset timeline as well. whitequark 2020-07-08 07:12:00 +0000
• 90e2a991f0 back.pysim: simplify. NFC. whitequark 2020-07-08 06:29:34 +0000
• 94faf497ba back.pysim: extract timeline handling to class _Timeline. NFC. whitequark 2020-07-08 06:04:50 +0000
• d3d210eaee back.pysim: extract simulator commands to sim._cmds. NFC. whitequark 2020-07-08 05:42:33 +0000
• e435a21715 back.pysim: simplify. NFC. whitequark 2020-07-08 03:55:09 +0000
• 659b0e8189
  hdl.ast: don't inherit Shape from NamedTuple. awygle 2020-07-06 22:17:03 -0700
• cee43f0de1 back.pysim: simplify. whitequark 2020-07-07 04:29:13 +0000
• c9030eb3cd back.pysim: simplify. NFC. whitequark 2020-07-07 04:19:05 +0000
• db4529a178 back.pysim: simplify. NFC. whitequark 2020-07-07 04:09:10 +0000
• 2efeb05c63 back.pysim: synchronize waveform writing with cxxrtl. whitequark 2020-07-07 04:06:06 +0000
• e012e62ade back.pysim: synchronize terms with cxxrtl. NFC. whitequark 2020-07-07 02:35:04 +0000
• c9ac85a045 back.pysim: simplify. NFC. whitequark 2020-07-07 02:14:06 +0000