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Author SHA1 Message Date
whitequark 38b75ba4bc back.cxxrtl: actualize Yosys version requirement. 2020-08-26 09:16:46 +00:00
whitequark 00026c6e4a hdl.ast: avoid unnecessary sign padding in ArrayProxy. 
Before this commit, ArrayProxy would add sign padding (an extra bit)
a homogeneous array of signed values, or an array where all unsigned
values are smaller than the largest signed one. After this commit,
ArrayProxy would only add padding in arrays with mixed signedness
where all signed values are smaller or equal in size to the largest
unsigned value.

Fixes #476.

Co-authored-by: Pepijn de Vos <pepijndevos@gmail.com>
 2020-08-26 07:07:48 +00:00
whitequark cb81618c28 sim._pyrtl: fix miscompilation of -(Const(0b11, 2).as_signed()). 
Fixes #473.
 2020-08-26 04:15:54 +00:00
whitequark 0802f943ba lib.cdc: in AsyncFFSynchronizer(), rename domain= to o_domain=. 
This is for consistency with other synchronizers.

Fixes #467.
 2020-08-26 03:19:13 +00:00
Robin Ole Heinemann 630c0fd99a vendor.lattice_machxo_2_3l: add SRAM svf generation 2020-08-24 14:41:14 +00:00
Mariusz Glebocki 4e208b0ac1 vendor: Add initial support for Symbiflow for Xilinx 7-series 2020-08-24 14:39:10 +00:00
Mariusz Glebocki 77616837e8 vendor.xilinx_7series: add _part property getter 2020-08-24 14:39:10 +00:00
Xiretza 15f150337f cli: Improve help texts 
545e49c2 added the option to export as CXXRTL, but the help texts for
the CLI options don't reflect this yet.
 2020-08-22 14:41:37 +00:00
awygle 73f672f57c
lib.fifo: add r_level and w_level to all FIFOs 2020-08-15 08:40:56 +00:00
Robin Ole Heinemann b86acdc601 vendor.lattice_{ecp5,machxo_2_3l}: specify impl-dir correctly 2020-08-10 17:52:47 +00:00
whitequark d964ba9cc4 build,vendor: never carry around parts of differential signals. 
When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
 2020-07-31 18:41:59 +00:00
whitequark c9662c5ff8 vendor.xilinx_{7series,ultrascale}: use BUFGCTRL rather than BUFGCE. 
Fixes #438 (again).
 2020-07-31 17:48:22 +00:00
Adam Greig 07dc163105
hdl.mem: cast reset value for transparent read ports to integer. 2020-07-30 07:05:18 +00:00
Jean THOMAS 20f9ab9d7a
nmigen.lib.scheduler: add RoundRobin. 2020-07-28 21:02:01 +00:00
Jacob Graves 8117ef6692
tests: fix remove unnecessary workaround for some unittest assertions. 2020-07-28 19:35:25 +00:00
whitequark c75fa45fd8 vendor.xilinx_{7series,ultrascale}: add SIM_DEVICE parameter. 
The parameter defaults to "ULTRASCALE", even when synthesizing for
7-series devices. This could lead to a simulation/synthesis mismatch,
and causes a warning.

Fixes #438.
 2020-07-23 16:38:28 +00:00
Jean THOMAS f7a8fcc94c
vendor.lattice_ecp5: add missing differential IO types. 2020-07-23 12:24:31 +00:00
whitequark 7aedb3e770 back.rtlil: lower maximum accepted wire size. 
In practice wires of just 100000 bits sometimes have unacceptable
performance with Yosys, so stick to Verilog's minimum limit of 65536
bits.
 2020-07-22 14:43:44 +00:00
whitequark 1321c4591d sim._pycoro: avoid spurious wakeups. 
This bug was introduced in commit e435a217.
 2020-07-22 14:32:45 +00:00
whitequark 0899ff366b compat.fhdl.bitcontainer: fix value_bits_sign(). 
This function was broken in commit 659b0e81; some downstream code
expects bits_sign to be e.g. indexable.
 2020-07-21 02:53:29 +00:00
whitequark d06add0aab back.rtlil: fix guard for division by zero. 
Oops... that should be checking the divisor, not the dividend. This
was discovered by running the test suite on cxxsim.
 2020-07-15 04:14:34 +00:00
whitequark ecb3a69d48 lib.cdc: fix typo. 
Co-authored-by: @ECP5-PCIe
 2020-07-13 23:53:15 +00:00
Jacob Lifshay 58f1d4bcb6
sim.pysim: write the next, not curr signal value to the VCD file 
This is a temporary fix for #429.
 2020-07-13 02:10:01 +00:00
whitequark 0a90aa1b17 sim.pysim: use VCD aliases to reduce space and time overhead. 
On Minerva SoC, this reduces VCD file size by about 35%, and reduces
runtime overhead of writing VCDs by 10% or less.
 2020-07-11 12:26:34 +00:00
whitequark 30e2f91176 sim: simplify. NFC. 2020-07-08 17:31:53 +00:00
whitequark d7a87fef42 back.pysim→sim.pysim; split into more manageable parts. 
This is necessary to add cxxrtl as an alternate simulation engine.
 2020-07-08 12:49:38 +00:00
whitequark 23da2fdda6 vendor.xilinx_{7series,ultrascale}: remove grade property. 
This was added in commit bfd4538d based on a misunderstanding of how
Xilinx part numbers work.
 * non-ultrascale 7-series parts don't have temperature grades;
 * ultrascale parts have temperature grade as a part of speed grade.
 2020-07-08 09:08:00 +00:00
whitequark 6d417568ad back.pysim: only extract signal names if VCD is requested. 
This commit also fixes an issue introduced in 2606ee33 that regressed
simulator startup time and bloated VCD files. (It's actually about
10% faster now than *before* the regression was introduced.)
 2020-07-08 08:33:45 +00:00
whitequark 3c3cfd48fb back.pysim: reset timeline as well. 
This is a bug that was introduced in 94faf497b.
 2020-07-08 08:19:29 +00:00
whitequark 90e2a991f0 back.pysim: simplify. NFC. 2020-07-08 06:31:04 +00:00
whitequark 94faf497ba back.pysim: extract timeline handling to class _Timeline. NFC. 2020-07-08 06:31:04 +00:00
whitequark d3d210eaee back.pysim: extract simulator commands to sim._cmds. NFC. 2020-07-08 05:42:33 +00:00
whitequark e435a21715 back.pysim: simplify. NFC. 2020-07-08 03:55:09 +00:00
awygle 659b0e8189
hdl.ast: don't inherit Shape from NamedTuple. 
Fixes #421.
 2020-07-07 05:17:03 +00:00
whitequark cee43f0de1 back.pysim: simplify. 
Compiled process names were never particularly useful (comments in
the source would make more sense for debugging), and coroutine
process names were actually source locations.
 2020-07-07 04:29:13 +00:00
whitequark c9030eb3cd back.pysim: simplify. NFC. 2020-07-07 04:19:05 +00:00
whitequark db4529a178 back.pysim: simplify. NFC. 2020-07-07 04:09:10 +00:00
whitequark 2efeb05c63 back.pysim: synchronize waveform writing with cxxrtl. 2020-07-07 04:09:02 +00:00
whitequark e012e62ade back.pysim: synchronize terms with cxxrtl. NFC. 2020-07-07 03:38:39 +00:00
whitequark c9ac85a045 back.pysim: simplify. NFC. 2020-07-07 03:38:39 +00:00
whitequark 8f6eab0f6c back.pysim: simplify. NFC. 2020-07-07 03:38:39 +00:00
whitequark 23758e30bc Remove everything deprecated in nmigen 0.2. 2020-07-07 03:38:39 +00:00
Konrad Beckmann d4946b060a vendor.lattice_ecp5: Add support for io with xdr=7 
This adds support for IOs with xdr=7 using the
IODDR71B and ODDR71B primitives.
 2020-07-06 16:12:07 +00:00
Konrad Beckmann 981e674081 vendor.lattice_ecp5: Add support for io with xdr=4 
This adds support for IOs with xdr=4 using the
IDDRX2F and ODDRX2F primitives.
 2020-07-06 16:12:07 +00:00
whitequark fd5ee548b6 test: remove FHDLTestCase.assertRaisesRegex. 
This method is only there because I misunderstood the documentation
of unittest.
 2020-07-02 22:50:20 +00:00
whitequark 8dd28fecc6 compat.fhdl.specials: fix handling of tristate (i=None) pins. 
Fixes #406.
 2020-07-02 22:22:44 +00:00
whitequark 369bc3e307 _yosys→_toolchain.yosys 2020-07-02 18:26:08 +00:00
whitequark 6bfff25e76 vendor: yosys is not a required tool for proprietary toolchains. 
Since commit b9799b4c, the discovery mechanism for the Yosys required
to produce Verilog is different from the usual require_tool(); namely
it is possible to produce Verilog without a `yosys` binary on PATH.

Fixes #419.
 2020-07-02 18:13:54 +00:00
whitequark 126f0be731 Gracefully handle missing dependencies. 
Some people's workflows involve not using `pip`. This is not
a recommended way to use nMigen, but is prevalent enough for good
enough reason that we try to keep them working anyway.
 2020-07-01 07:00:02 +00:00
whitequark 399b8f9863 Add (heavily work in progress) documentation. 
To render correctly, the docs require:
 * pygments/pygments#1441
 2020-06-30 22:21:16 +00:00