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Author SHA1 Message Date
whitequark f0c1c2cfeb build.dsl: allow assertions on subsignal widths. 
This is useful when building abstractions around resources where
the pin names are user-specified.

Fixes #129.
 2019-07-08 10:42:06 +00:00
whitequark a7fbff94d8 hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain. 
Fixes #125.
 2019-07-08 10:26:49 +00:00
whitequark 5c63177fc2 test: generate examples to verilog as part of unit tests. 
This is to make sure 806a62c2 doesn't happen again.
 2019-07-08 10:12:26 +00:00
whitequark da1f58b7ae hdl.dsl: further clarify error message for incorrect nesting. 
Fixes #133.
 2019-07-07 01:03:59 +00:00
whitequark cb8be4a1b0 hdl.dsl: clarify error message for incorrect nesting. 
Refs #133.
 2019-07-07 00:59:57 +00:00
whitequark 3388b5b085 hdl.dsl: gracefully handle FSM with no states. 2019-07-07 00:59:34 +00:00
whitequark b471e33d7f build.res: detect physical conflicts earlier. 
This is useful for two reasons:
  1. nMigen can provide better error messages than the platform and
     do it earlier in the build pipeline.
  2. Many platforms handle diffpairs by only constraining the P pin;
     the N pin is completely ignored. If this is undetected,
     downstream users (human or software) can rely on this
     information assuming it is correct and introduce more errors.
     (Of course, this will not catch every mistake, but the most
     common is a copy-paste issue, and that will handle it.)

Fixes #124.
 2019-07-03 15:07:44 +00:00
whitequark 0ab215e5ed hdl.ast: recognize a Enum used as decoder and format it better. 2019-07-02 19:34:44 +00:00
whitequark 6b843b5be6 hdl.rec: implement slicing by component names. 
Fixes #121.
 2019-07-02 17:46:53 +00:00
whitequark 34f110100a hdl.rec: implement Record.like. 
Fixes #120.
 2019-07-02 17:46:53 +00:00
whitequark 94e8f479a5 hdl.mem: use read_port(domain="comb") for asynchronous read ports. 
This avoids the absurdity of the combination of arguments that is
read_port(domain="sync", synchronous=True).

Fixes #116.
 2019-07-01 19:56:49 +00:00
whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
 2019-06-28 04:37:08 +00:00
whitequark 48d4ee4031 hdl.ir, back.rtlil: allow specifying attributes on instances. 
Fixes #107.
 2019-06-28 04:14:38 +00:00
whitequark e5e23644a4 hdl.{ast,dst}: directly represent RTLIL default case. 
This makes RTLIL mildly nicer:

 casez ({ \$5 , \$3 , \$1  })
   3'bzz1:
       \$next\o  = \$7 ;
   3'bz1z:
       \$next\o  = \$9 ;
   3'b1zz:
       \$next\o  = \$11 ;
-  3'bz:
+  default:
       { \$next\co , \$next\o  } = \$13 ;
 endcase
 2019-06-25 22:01:14 +00:00
whitequark e52b15d236 hdl.ast: add name_suffix=".." option to Signal.like(). 
This simplifies creation of related signals with nice names during
metaprogramming, e.g.

  def make_ff(m, sig):
      sig_ff = Signal.like(sig, name_suffix="_ff")
      m.d.sync += sig_ff.eq(sig)
      return sig_ff
 2019-06-12 22:26:57 +00:00
whitequark efb2d773c3 build.{dsl,res,plat}: add PinsN and DiffPairsN. 2019-06-12 14:42:39 +00:00
whitequark ad1a40c934 hdl.ast: implement values with custom lowering. 2019-06-11 07:01:44 +00:00
whitequark 066dd799e8 back.pysim: check for a clock being added twice. 
This commit adds a best-effort error for a common mistake of adding
a clock driving the same domain twice, such as a result of
a copy-paste error.

Fixes #27.
 2019-06-11 03:54:22 +00:00
whitequark 58e39f90ce hdl.mem: coerce memory init values to integers. 
The coercion is carefully chosen to accept (other than normal ints)
instances of e.g. np.int64, but reject instances of e.g. float.
See https://stackoverflow.com/a/48940855/254415 for details.

Fixes #93.
 2019-06-11 03:38:44 +00:00
whitequark b45c5119f5 build.res: allow querying frequency of a previously constrained clock. 2019-06-05 12:51:53 +00:00
whitequark c9879c795b build.{dsl,res,plat}: apply clock constraints to signals, not resources. 
This adds the Clock() build DSL element, and adds a resource manager
function add_clock_constraint() that takes a Pin or a Signal.
Note that not all platforms, in particular not any nextpnr platforms
at the moment, can add constraints on arbitrary signals.

Fixes #86.
 2019-06-05 08:52:30 +00:00
whitequark ab3f103e5a build.dsl: replace extras= with Attrs(). 
This change proved more tricky than expected due to downstream
dependencies, so it also includes some secondary refactoring.
 2019-06-05 07:02:08 +00:00
whitequark 39ca0e6fa6 compat.fhdl.module: CompatModule should be elaboratable. 
Fixes #83.
 2019-06-04 11:11:31 +00:00
whitequark 4310254103 build.res: use ConstraintError iff a constraint invariant is violated. 
In particular don't use it for type errors.
 2019-06-04 11:00:11 +00:00
whitequark 51c03ca391 hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}. 2019-06-04 10:26:01 +00:00
whitequark 9f643ce005 Clean up imports. 
This commit:
  * moves lists of universally useful imports from `nmigen` to
    `nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
  * replaces lots of imports from individual parts of `nmigen.hdl`
    with a star import from `nmigen.hdl`;
  * replaces imports in tests with what we expect downstream code
    to use;
  * adds some missing imports in `nmigen.formal`.
 2019-06-04 08:18:50 +00:00
whitequark ed64880cc4 build.{plat,res}: add support for connectors. 
Fixes #77.
 2019-06-03 15:02:15 +00:00
whitequark a013eb1f59 build.dsl: add support for connectors. 2019-06-03 13:47:00 +00:00
whitequark 41adcc3f97 vendor.fpga.lattice_ice40: implement differential input buffers. 2019-06-03 08:38:12 +00:00
whitequark b42043f764 lib.io: add i_clk and o_clk to pin layout with xdr>=1. 2019-06-03 07:43:31 +00:00
whitequark a1940c5528 hdl.rec: unbreak hasattr(rec, ...). 
hasattr() requires that AttributeError be raised. Change __getitem__
to raise AttributeError, too, since it is fundamentally just sugar
for getattr().
 2019-06-03 07:43:31 +00:00
whitequark 6fae06aea9 build.{dsl,plat,res}: allow dir="oe". 
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.

E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
 2019-06-03 04:42:55 +00:00
whitequark 1eee7cd76f lib.io: allow dir="oe". 
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.

E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
 2019-06-03 04:28:53 +00:00
whitequark 9ba2efd86b build.{res,plat}: use xdr=0 as default, not xdr=1. 
The previous behavior was semantically incorrect.
 2019-06-03 03:36:32 +00:00
whitequark cd6488c782 build.res: allow requesting raw ports, with dir="-". 
This provides an escape hatch for the case where the nMigen platform
code is not flexible enough, and a IO buffer primitive needs to be
instantiated directly.
 2019-06-03 03:36:32 +00:00
whitequark c30617fc05 lib.io: allow Pin(xdr=0), representing a combinatorial I/O buffer. 2019-06-03 03:36:32 +00:00
whitequark dc17d06fe9 vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras. 
The PULLUP and PULLUP_RESISTOR extras are representable in the PCF
file. The IO_STANDARD extra, however, can only be an SB_IO parameter.
 2019-06-03 02:51:59 +00:00
whitequark c6a0761b3a hdl.ir: accept LHS signals like slices as Instance io ports. 
This is unlikely to work with anything except Slice and Cat, but
there's no especially good place to enforce it. (Maybe in Instance?)
 2019-06-03 02:39:14 +00:00
whitequark b8a61edc2f hdl.dsl: allow adding submodules with computed name, like with domains. 2019-06-03 02:22:55 +00:00
whitequark b64a31255c hdl.ir: accept expanded (kind, name, value) tuples in Instance. 
This is useful for e.g. programmatically generating parameters
without having to mess with kwargs dicts.
 2019-06-03 02:12:01 +00:00
whitequark fb01854372 build.{res,plat}: propagate extras to pin fragment factories. 
This is necessary because on some platforms, like iCE40, extras
become parameters on an IO primitive, since the constraint file
format is not expressive enough for all of them.
 2019-06-03 01:58:43 +00:00
whitequark 98497b2075 build.dsl: require a dict for extras instead of a stringly array. 
Fixes #72.
 2019-06-02 23:36:21 +00:00
whitequark 53ddff9f33 build.res: always return a Pin record. 
In the simple cases, a Pin record consisting of exactly one field
is equivalent in every way to this single field. In the more complex
case however, it can be used as a record, making the code more robust
such that it works with both bidirectional and unidirectional pins.
 2019-06-01 16:41:30 +00:00
whitequark 8c1b5a26b3 build.res: accept a list of clocks in ConstraintManager constructor. 2019-06-01 15:41:41 +00:00
Jean-François Nguyen d393c5ec64 build.res: add ConstraintManager. 2019-05-26 01:26:58 +00:00
whitequark 3a9fe31133 build.dsl: make Pins and DiffPairs iterable. 
Returns pin names.
 2019-05-25 22:43:48 +00:00
whitequark 48145cee02 build.dsl: improve repr of Pins() and DiffPairs(). 2019-05-25 22:43:23 +00:00
whitequark 2b7dc37ffe hdl.rec: allow providing fields during construction. 
This allows creating records populated with e.g. signals with custom
names, or sub-records that are instances of Record subclasses.
 2019-05-25 22:06:56 +00:00
whitequark 3392708e2b Consider Instances a part of containing fragment for use-def purposes. 
Fixes #70.
 2019-05-25 20:13:43 +00:00
whitequark c337246fc5 hdl.ir: when adding sync domain to a design, also add it to ports. 
Otherwise we end up in a situation where the examples don't have
clk and rst as ports, which is not nice.

Fixes #67.
 2019-05-15 06:44:50 +00:00
whitequark 39bc59c924 hdl.ir: during port propagation, defs should take priority over uses. 2019-05-13 15:34:13 +00:00
whitequark 958cb18b88 hdl.ir: only pull explicitly specified ports to toplevel, if any. 
Fixes #30.
 2019-05-12 05:21:23 +00:00
Jean-François Nguyen dd5bd1c88d build: add DSL for defining platform resources. 2019-04-24 11:49:01 +00:00
whitequark 585514e6ed hdl.ir: rework named port handling for Instances. 
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.

While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
 2019-04-22 07:46:47 +00:00
whitequark 44711b7d08 hdl.ir: detect elaboratables that are created but not used. 
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.

Fixes #3.
 2019-04-21 08:52:57 +00:00
whitequark 360bc9b5b4 hdl.ast: improve tests for exceptional conditions. 2019-04-21 07:20:00 +00:00
whitequark 33f9bd2a1d hdl.ast: accept Signals with identical min/max bounds. 
And produce a 0-bit signal.

Fixes #58.
 2019-04-21 07:16:59 +00:00
whitequark ce1eff5464 hdl.rec: implement Record.connect. 
Fixes #31.
 2019-04-21 06:37:08 +00:00
whitequark 611c25f909 hdl.rec: fix slicing of records. 2019-04-19 19:55:39 +00:00
whitequark 287a0531b3 lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin. 2019-04-15 16:27:23 +00:00
whitequark 0a2a7025a6 hdl.xfrm: allow using FragmentTransformer on any elaboratable. 
Fixes #29.
 2019-04-10 00:23:11 +00:00
whitequark a74cacdc69 hdl.ast: handle a common typo, such as Signal(1, True). 2019-04-03 14:59:01 +00:00
whitequark c9c9307a5e test_sim: add missing add_process(). 
Fixes #43.
 2019-03-28 17:50:14 +00:00
anuejn 3c95299c4e hdl.rec: separate record and signal name with __, not _. 
This makes names of signals within records less ambiguous, in case
they themselves have underscores within them.
 2019-03-25 14:26:00 +00:00
whitequark 8ee6bd80ff hdl.ir: raise a more descriptive error on non-elaboratable object. 2019-02-14 20:52:42 +00:00
whitequark f44ca291c1 lib.cdc: add ResetSynchronizer. 2019-01-26 18:07:59 +00:00
whitequark 4bf80a6e33 compat: suppress deprecation warnings that are internal or during test. 2019-01-26 15:43:00 +00:00
whitequark 7890c0adc8 test.compat: reenable tests converting to Verilog. 2019-01-26 15:29:09 +00:00
whitequark 4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark 4922a73c5d test.compat: import tests from Migen as appropriate. 
test_signed and test_coding are adjusted slightly to account for
differences in comb propagation between the simulators; we might want
to revert that eventually.
 2019-01-26 01:01:03 +00:00
whitequark f71e0fffbb hdl.ast: fix shape calculation for *. 
This was carried over from Migen, and is wrong there too.
Counterexample: 1'sd-1 * 4'sd-4 = 4'sd-4 (but should be 5'sd4).
 2019-01-26 00:56:40 +00:00
whitequark 7b25665fde back.pysim: fix behavior of initial cycle for sync processes. 
The current behavior was introduced in 65702719, which was a wrong
fix for an issue that was actually fixed in 12e04e4e. This commit
effectively reverts 65702719 and 1782b841.
 2019-01-25 20:37:56 +00:00
whitequark e33580cf4c lib.fifo: add AsyncFIFO and AsyncFIFOBuffered. 2019-01-21 16:02:46 +00:00
whitequark 12e04e4ee5 back.pysim: wake up processes before ever committing any values. 
Otherwise, the contract of the simulator to sync processes is not
always fulfilled.
 2019-01-21 16:00:25 +00:00
whitequark b6cff2c098 lib.coding: add GrayEncoder and GrayDecoder. 
Unlike the Migen ones, these are purely combinatorial.
 2019-01-20 02:20:34 +00:00
whitequark 9de9272709 lib.fifo: use memory in the FIFO model. 
This is unfortunately more complicated, but results in a much faster
proof.
 2019-01-19 09:27:56 +00:00
whitequark 6ea0a12dd4 lib.fifo: use model equivalence to simplify formal specification. 
This is unfortunately slow, and should probably be using theory
of arrays.
 2019-01-19 09:27:56 +00:00
whitequark c5d67b0461 hdl.xfrm: mark internal registers used in lowering Sample(). 2019-01-19 07:27:32 +00:00
whitequark 97b990272e lib.fifo: formally verify FIFO contract. 2019-01-19 00:52:56 +00:00
whitequark 5a831ce31c lib.fifo: add basic formal specification. 2019-01-17 05:40:25 +00:00
whitequark fa8e876356 hdl.ast: allow sampling ClockSignal, ResetSignal. 2019-01-17 05:23:06 +00:00
whitequark 8c96675580 hdl.ast: add Past, Stable, Rose, Fell. 2019-01-17 04:31:27 +00:00
whitequark 198efcad31 hdl.xfrm: add SampleLowerer. 2019-01-17 01:41:02 +00:00
whitequark b3de114d67 hdl.ast: add Sample. 2019-01-17 01:36:27 +00:00
whitequark b78a2be9f6 lib.fifo: port sync FIFO queues from Migen. 2019-01-16 17:20:38 +00:00
whitequark cb2f18ee37 hdl.ast: fix naming of Signal.like() signals when tracer fails. 2019-01-16 17:20:38 +00:00
whitequark b534e92dd5 hdl.ir: allow explicitly requesting flattening. 2019-01-14 17:04:23 +00:00
whitequark 011bf2258e hdl: make ClockSignal and ResetSignal usable on LHS. 
Fixes #8.
 2019-01-14 15:38:16 +00:00
whitequark 664b4bcb3a hdl.dsl: cases wider than switch test value are unreachable. 
In 3083c1d6 they were erroneously fixed via truncation.
 2019-01-13 08:51:49 +00:00
whitequark 3083c1d6dd hdl.dsl: accept (but warn on) cases wider than switch test value. 
Fixes #13.
 2019-01-13 08:46:28 +00:00
whitequark cbf7bd6e31 back.pysim: handle non-driven, non-port signals. 
Fixes #20.
 2019-01-13 08:31:38 +00:00
William D. Jones 2412650f56 hdl.dsl: Support Assert and Assume where an Assign can occur. 2019-01-02 11:17:39 +00:00
whitequark 3c07d8d52c hdl.rec: include record name in error message. 2019-01-01 03:39:12 +00:00
whitequark 031a9e2616 hdl.rec: use a helpful error on unknown field reference. 2019-01-01 03:35:34 +00:00
whitequark d78e6c155b hdl.mem: add DummyPort, for testing and verification. 2019-01-01 03:08:10 +00:00
whitequark 39eb2e8fa7 lib.cdc: fix tests to actually run. 2018-12-29 15:02:44 +00:00
whitequark 849c649259 back.pysim: warn if simulation is not run. 
This would have prevented 3ea35b85.
 2018-12-29 15:02:04 +00:00
whitequark 92a96e1644 hdl.rec: add basic record support. 2018-12-28 13:22:10 +00:00
whitequark 3ea35b8566 lib.coding: fix tests to actually run, and fix code to fix tests. 2018-12-27 21:45:55 +00:00
whitequark 470d66934f hdl.dsl: add support for fsm.ongoing(). 2018-12-27 16:19:01 +00:00