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Author SHA1 Message Date
whitequark f6f0a7b692 lib.fifo: simplify. NFC. 2019-09-21 06:15:11 +00:00
whitequark a1bc2bbeb0 lib.fifo: fix doc typo. NFC. 2019-09-20 19:54:27 +00:00
whitequark f9b9c17a16 lib.fifo: work around Yosys issue with handling of \TRANSPARENT. 
Because of YosysHQ/yosys#1390, using a transparent port in AsyncFIFO,
instead of being a no-op (as the semantics of \TRANSPARENT would
require it to be in this case), results in a failure to infer BRAM.

This can be easily avoided by using a non-transparent port instead,
which produces the desirable result with Yosys. It does not affect
the semantics on Xilinx platforms, since the interaction between
the two ports in case of address collision is undefined in either
transparent (WRITE_FIRST) or non-transparent (READ_FIRST) case, and
the data out of the write port is not used at all.

Fixes #172.
 2019-09-20 19:54:27 +00:00
whitequark 4b3a068b15 hdl.mem: use 1 as reset value for ReadPort.en. 
This is necessary for consistency, since for transparent read ports,
we currently do not support .en at all (it is fixed at 1) due to
YosysHQ/yosys#760. Before this commit, changing port transparency
would require adding or removing an assignment to .en, which is
confusing and error-prone.

Also, most read ports are always enabled, so this behavior is also
convenient.
 2019-09-20 19:51:13 +00:00
whitequark 91ef2f58e3 vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals. 
Fixes #88.
 2019-09-20 16:26:27 +00:00
whitequark 378e924280 hdl.ast: rename nbits to width. 
Also, replace `bits, sign = x.shape()` with more idiomatic
`width, signed = x.shape()`.

This unifies all properties corresponding to `len(x)` to `x.width`.
(Not all values have a `width` property.)

Fixes #210.
 2019-09-20 15:36:25 +00:00
Darrell Harmon af7224de5d vendor.xilinx_{7series,spartan3_6}: specialize MultiReg. 
Vivado/ISE would otherwise infer an SRL16 from a MultiReg in some cases.
 2019-09-20 15:13:27 +00:00
Emily f2550021c3 setup: improve repository detection. 2019-09-20 14:01:18 +00:00
Emily 6f12272533 setup: add setuptools dependency. 2019-09-20 14:01:18 +00:00
whitequark 276e9c2fad test.test_lib_fifo: fix typo. 2019-09-20 11:53:05 +00:00
whitequark 7f6b3f93f5 back.pysim: fix simulation of Value.xor(). 2019-09-20 10:12:59 +00:00
whitequark 4777a7b3a2 hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns. 
Fixes #207.
 2019-09-16 19:22:12 +00:00
whitequark e8f79c5539 hdl.ast: add Value.matches(), accepting same language as Case(). 
Fixes #202.
 2019-09-14 21:06:12 +00:00
whitequark f292a1977c hdl.dsl: improve error messages for Case(). 2019-09-14 20:58:19 +00:00
whitequark 32310aecad hdl.ast: add Value.xor, mapping to $reduce_xor. 
Fixes #147.
 2019-09-13 14:29:46 +00:00
whitequark b23a9794a4 hdl.ast: add Value.{any,all}, mapping to $reduce_{or,and}. 
Refs #147.
 2019-09-13 13:14:52 +00:00
whitequark bdb70ad45f lib.fifo: adjust for new CDC primitive conventions. 
Fixes #97.
 2019-09-13 12:36:51 +00:00
whitequark da4b810fe1 lib.fifo: adjust properties to have consistent naming. 2019-09-13 12:33:41 +00:00
whitequark 9ea3ff7ae2 build.plat: bypass tool detection if NMIGEN_*_env is set. 
It's not practical to detect tools within the toolchain environment
for various reasons, so just assume the tools are there if the user
says they are.

Before this commit, the tools would be searched outside the toolchain
environment, which of course would always fail for Vivado, ISE, etc.
 2019-09-12 21:56:48 +00:00
whitequark c8f8c09f29 vendor.xilinx_7series: Vivado requires bash on *nix as well. 2019-09-12 21:49:08 +00:00
whitequark 42805ad959 hdl.mem: use keyword-only arguments as appropriate. 2019-09-12 20:03:48 +00:00
whitequark b92e967b78 lib.fifo: make fwft a keyword-only argument. 
Because it accepts a boolean.
 2019-09-12 19:38:18 +00:00
whitequark 1c091e67a4 lib.fifo: remove SyncFIFO.replace. 
This obscure functionality was likely only ever used in old MiSoC
code, and doesn't justify the added complexity. It was also not
provided (and could not be reasonably provided) in SyncFIFOBuffered,
which made its utility extremely marginal.
 2019-09-12 19:16:57 +00:00
whitequark 2c34b1f947 README: update Yosys version requirement. 2019-09-12 14:33:38 +00:00
whitequark 2d2ab6e09d lib.cdc: make domain properties private. 
It is not correct to access domain properties from user code, because
it will not match the reality if DomainRenamer has been applied to
the module.
 2019-09-12 13:54:48 +00:00
whitequark 73244f2bd2 lib.io: style. NFC. 2019-09-12 13:51:18 +00:00
whitequark 9893e3c044 lib.cdc: adjust ResetSynchronizer for new CDC primitive conventions. 
Refs #97.
 2019-09-12 13:48:45 +00:00
whitequark 8f659b6cd6 lib.cdc: adjust MultiReg for new CDC primitive conventions. 
Refs #97.
 2019-09-12 13:48:24 +00:00
whitequark 8c30147e39 build.plat,vendor: allow clock constraints on arbitrary signals. 
Currently only done for Synopsys based toolchains (i.e. not nextpnr).

Refs #88.
 2019-09-11 23:35:43 +00:00
whitequark d1779bdb59 back: return name map from convert_fragment(). 2019-09-11 23:22:12 +00:00
whitequark 7342662bee hdl.ast: warn if reset value is truncated. 
Fixes #183.
 2019-09-10 07:26:34 +00:00
Darrell Harmon 27cedf4302 vendor.lattice_ecp5: pass ecppack_opts to ecppack. 2019-09-10 03:32:36 +00:00
whitequark 9b398b502e hdl.ast: check type of Sample(domain=...). 
Fixes #199.
 2019-09-08 23:55:05 +00:00
whitequark 3f6abc0b7a hdl.dsl: add Default(), an alias for Case() with no arguments. 
Fixes #197.
 2019-09-08 12:24:18 +00:00
whitequark eb04a2509e hdl.mem,lib,examples: use Signal.range(). 2019-09-08 12:19:13 +00:00
whitequark ccfbccc044 hdl.ast: add Signal.range(...), to replace Signal(min=..., max=...). 
Fixes #196.
 2019-09-08 12:10:31 +00:00
whitequark 5e9587bbbd Remove nmigen.lib from prelude. 
Currently it's just MultiReg, and there's no particularly good reason
to privilege this specific CDC primitive so much.
 2019-09-06 06:53:06 +00:00
whitequark 38831abdb4 Fix .gitignore. 2019-09-06 05:30:22 +00:00
whitequark 284b533995 setup: replace versioneer with setuptools_scm. 
Has the same problems with git-archive but is much less invasive.
 2019-09-06 05:20:42 +00:00
whitequark 943ce317af hdl.ast,back.rtlil: implement Cover. 
Fixes #194.
 2019-09-03 01:32:24 +00:00
whitequark 2e20622046 hdl.cd: add negedge clock domains. 
Fixes #185.
 2019-08-31 22:05:48 +00:00
Emily c4e8ac734f _toolchain,build.plat,vendor.*: add required_tools list and checks. 2019-08-31 00:05:47 +00:00
whitequark 4e91710933 vendor.lattice_ecp5: drive GSR synchronous to user clock by default. 
Fixes #167.
 2019-08-30 14:26:49 +00:00
whitequark a4b58cbf3a build.dsl: allow both str and int resource attributes. 2019-08-30 08:35:52 +00:00
Emily 98278a044d test.tools: use _toolchain.get_tool. 2019-08-28 11:52:16 +00:00
whitequark b14f5572d8 _toolchain: new module, for injecting dependencies in e.g. Nix. 2019-08-28 11:32:18 +00:00
whitequark 2168ff512b back.verilog: bump Yosys version requirement to 0.9. 
Fixes #55.
 2019-08-26 09:59:40 +00:00
whitequark b4b5d9e2ef vendor.lattice_ecp5: revert default toolchain to Trellis. 
This was unintentionally changed in 7fc1058e.
 2019-08-25 08:07:00 +00:00
whitequark 72cf4ca991 back.pysim: implement sim.add_clock(if_exists=True). 2019-08-23 08:53:48 +00:00
whitequark 906385c7f8 back.pysim: don't crash when trying to drive a nonexistent domain clock. 2019-08-23 08:37:59 +00:00