This is useful for two reasons:
1. nMigen can provide better error messages than the platform and
do it earlier in the build pipeline.
2. Many platforms handle diffpairs by only constraining the P pin;
the N pin is completely ignored. If this is undetected,
downstream users (human or software) can rely on this
information assuming it is correct and introduce more errors.
(Of course, this will not catch every mistake, but the most
common is a copy-paste issue, and that will handle it.)
Fixes#124.
In compat.fhdl.module, we already default to "sync" as the default
clocked domain. Using "sys" in memories only would be inconsistent
and result in more bugs.
According to RTLIL semantics (that was undocumented before today),
the only purpose of `sync always` is to enable inference of latches,
because there is no other way to express them in terms of RTLIL
processes without ending up with a combinatorial loop. But, nMigen
specifically avoids latches, so this is not necessary.
This change results in major improvements in Verilog readability.
See also #98.
Commit 300d47ca introduced the same bug commit 779f3ee9 was trying to
avoid, but now only in the simulator. Since the names in simulator
don't have to make any sense, just use DUID to generate them.
This was rewritten to use Yosys cells in 779f3ee9 to avoid leaking
the interior clock domain, but the simulator doesn't understand Yosys
cells. So, use the old implementation in the simulator.
Such clock domains will "leak" into the enclosing scope, which is
generally undesirable. Also, this is instructive for a platform
overriding the behavior, since it provides guidance on how to
correctly instantiate platform-specific flops.
I've considered also doing this for MultiReg(), but it is very
challenging in presence of non-reset-less CDC FFs, since Yosys'
$dffsr primitive has separate set and clear inputs, and reshuffling
the reset value for those results in quite a bit of additional logic.
(That said, it might have to be done anyway, precisely because
letting Yosys generate this additional logic might prove too much
for the toolchain to cope with, and again, platform-independent
code should provide guidance to platform-specific code.)
This means that instead of:
with m.Case(0b00):
<body>
with m.Case(0b01):
<body>
it is legal to write:
with m.Case(0b00, 0b01):
<body>
with no change in semantics, and slightly nicer RTLIL or Verilog
output.
Fixes#103.
Do this to make sure all buffers, tristate/differential or not, are
instantiated the exact same way, and are subject to the same set of
toolchain bugs, if any.
Before this commit, in some cases there will be an inverter, which is
not allowed on an FDCE with IOB attribute set to true, as it will
interfere with packing.
This simplifies creation of related signals with nice names during
metaprogramming, e.g.
def make_ff(m, sig):
sig_ff = Signal.like(sig, name_suffix="_ff")
m.d.sync += sig_ff.eq(sig)
return sig_ff
This commit adds a best-effort error for a common mistake of adding
a clock driving the same domain twice, such as a result of
a copy-paste error.
Fixes#27.
The coercion is carefully chosen to accept (other than normal ints)
instances of e.g. np.int64, but reject instances of e.g. float.
See https://stackoverflow.com/a/48940855/254415 for details.
Fixes#93.
This adds the Clock() build DSL element, and adds a resource manager
function add_clock_constraint() that takes a Pin or a Signal.
Note that not all platforms, in particular not any nextpnr platforms
at the moment, can add constraints on arbitrary signals.
Fixes#86.
Right now the device name in the board file is just the option
nextpnr uses, but that's overnormalized and doesn't quite match
the chip names used elsewhere. It is even worse for ECP5 in terms
of mismatch with chip names, and for ECP5 we need to support other
toolchains as well, so let's handle this uniformly everywhere.
The iCE40 programmers are also moved, since they're board-specific.
(It looks like iceprog isn't, but it only works with Lattice
evaluation kits.)
Fixes#80.
This commit:
* moves lists of universally useful imports from `nmigen` to
`nmigen.hdl` and `nmigen.lib`, reimporting them in `nmigen`;
* replaces lots of imports from individual parts of `nmigen.hdl`
with a star import from `nmigen.hdl`;
* replaces imports in tests with what we expect downstream code
to use;
* adds some missing imports in `nmigen.formal`.
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.
E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
Although a dir="oe" pin is generally equivalent to dir="io" pin with
the i* signal(s) disconnected, they are not equivalent, because some
pins may not be able to support input buffers at all, either because
there are no input buffers, or because the input buffers are consumed
by some other resource.
E.g. this can happen on iCE40 when the input buffer is consumed by
a PLL.
