whitequark
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cb2f18ee37
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hdl.ast: fix naming of Signal.like() signals when tracer fails.
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2019-01-16 17:20:38 +00:00 |
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whitequark
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b534e92dd5
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hdl.ir: allow explicitly requesting flattening.
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2019-01-14 17:04:23 +00:00 |
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whitequark
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011bf2258e
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hdl: make ClockSignal and ResetSignal usable on LHS.
Fixes #8.
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2019-01-14 15:38:16 +00:00 |
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whitequark
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664b4bcb3a
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hdl.dsl: cases wider than switch test value are unreachable.
In 3083c1d6 they were erroneously fixed via truncation.
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2019-01-13 08:51:49 +00:00 |
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whitequark
|
3083c1d6dd
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hdl.dsl: accept (but warn on) cases wider than switch test value.
Fixes #13.
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2019-01-13 08:46:28 +00:00 |
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whitequark
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cbf7bd6e31
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back.pysim: handle non-driven, non-port signals.
Fixes #20.
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2019-01-13 08:31:38 +00:00 |
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|
William D. Jones
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2412650f56
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hdl.dsl: Support Assert and Assume where an Assign can occur.
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2019-01-02 11:17:39 +00:00 |
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whitequark
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3c07d8d52c
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hdl.rec: include record name in error message.
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2019-01-01 03:39:12 +00:00 |
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whitequark
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031a9e2616
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hdl.rec: use a helpful error on unknown field reference.
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2019-01-01 03:35:34 +00:00 |
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whitequark
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d78e6c155b
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hdl.mem: add DummyPort, for testing and verification.
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2019-01-01 03:08:10 +00:00 |
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whitequark
|
39eb2e8fa7
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lib.cdc: fix tests to actually run.
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2018-12-29 15:02:44 +00:00 |
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whitequark
|
849c649259
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back.pysim: warn if simulation is not run.
This would have prevented 3ea35b85.
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2018-12-29 15:02:04 +00:00 |
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whitequark
|
92a96e1644
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hdl.rec: add basic record support.
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2018-12-28 13:22:10 +00:00 |
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whitequark
|
3ea35b8566
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lib.coding: fix tests to actually run, and fix code to fix tests.
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2018-12-27 21:45:55 +00:00 |
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|
whitequark
|
470d66934f
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hdl.dsl: add support for fsm.ongoing().
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2018-12-27 16:19:01 +00:00 |
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whitequark
|
528747703d
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lib.coding: port from Migen.
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2018-12-26 13:19:34 +00:00 |
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|
whitequark
|
fe8cb55204
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lib.cdc: add tests for MultiReg.
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2018-12-26 12:58:30 +00:00 |
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|
whitequark
|
35a44f017f
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hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.
|
2018-12-26 12:42:43 +00:00 |
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whitequark
|
934546e633
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hdl.dsl: provide generated values for FSMs.
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2018-12-26 12:39:05 +00:00 |
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whitequark
|
040811c2e5
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hdl.ir: add an API for retrieving generated values, like FSM signal.
This is useful for tests.
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2018-12-26 12:35:35 +00:00 |
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whitequark
|
54e3195dcb
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hdl.dsl: implement FSM.
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2018-12-26 08:55:04 +00:00 |
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|
whitequark
|
98f554aa08
|
hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
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2018-12-24 02:17:28 +00:00 |
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whitequark
|
1c7c75a254
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hdl.xfrm: implement SwitchCleaner, for pruning empty switches.
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2018-12-24 02:02:59 +00:00 |
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whitequark
|
621dddebfd
|
hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
|
2018-12-22 22:19:14 +00:00 |
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whitequark
|
68dae9f50e
|
hdl.ir: flatten hierarchy based on memory accesses, too.
|
2018-12-22 21:43:46 +00:00 |
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|
whitequark
|
ae0cb48fbb
|
hdl.xfrm: implement LHSGroupAnalyzer.
|
2018-12-22 06:58:24 +00:00 |
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|
whitequark
|
f6772759c8
|
hdl.ir: fix port propagation between siblings, in the other direction.
|
2018-12-22 00:31:31 +00:00 |
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|
whitequark
|
913339c04a
|
hdl.ir: fix port propagation between siblings.
|
2018-12-21 23:53:18 +00:00 |
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|
whitequark
|
fa2af27bb0
|
hdl.mem: ensure transparent read port model has correct latency.
|
2018-12-21 13:01:08 +00:00 |
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|
whitequark
|
48d13e47ec
|
back.pysim: handle out of bounds ArrayProxy indexes.
|
2018-12-21 12:32:08 +00:00 |
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|
whitequark
|
e58d9ec74d
|
hdl.mem: add simulation model for memory.
|
2018-12-21 11:54:32 +00:00 |
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whitequark
|
c49211c76a
|
hdl.mem: add tests for all error conditions.
|
2018-12-21 06:07:16 +00:00 |
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|
whitequark
|
b0bd7bfaca
|
hdl.ir: correctly handle named output and inout ports.
|
2018-12-21 04:03:03 +00:00 |
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|
whitequark
|
f7fec804ec
|
ir: allow non-Signals in Instance ports.
|
2018-12-20 23:40:40 +00:00 |
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whitequark
|
dbbcc49a71
|
hdl.ast: Cat.{operands→parts}
|
2018-12-18 19:15:50 +00:00 |
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|
whitequark
|
4199674edd
|
back.pysim: implement *.
|
2018-12-18 18:02:21 +00:00 |
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|
whitequark
|
07e9cfa939
|
test.sim: add tests for sync functionality and errors.
|
2018-12-18 17:53:50 +00:00 |
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whitequark
|
c7f9386eab
|
fhdl.ir: add black-box fragments, fragment parameters, and Instance.
|
2018-12-17 22:55:39 +00:00 |
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|
whitequark
|
8d1639a5a8
|
hdl, back: add and use SignalSet/SignalDict.
|
2018-12-17 17:21:29 +00:00 |
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|
whitequark
|
015998eba9
|
hdl.dsl: add clock domain support.
|
2018-12-16 23:51:24 +00:00 |
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|
whitequark
|
d4e8d3e95a
|
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
|
2018-12-16 10:31:42 +00:00 |
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|
whitequark
|
d9579219ee
|
test.sim: generalize assertOperator. NFC.
|
2018-12-15 21:08:29 +00:00 |
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|
whitequark
|
20a04bca88
|
back.pysim: implement Part.
|
2018-12-15 20:58:06 +00:00 |
|
|
whitequark
|
54fb999c99
|
back.pysim: implement ArrayProxy.
|
2018-12-15 19:37:36 +00:00 |
|
|
whitequark
|
80c5343600
|
hdl.ast: implement Array and ArrayProxy.
|
2018-12-15 17:16:31 +00:00 |
|
|
whitequark
|
c6e7a93717
|
hdl: appropriately rename tests. NFC.
|
2018-12-15 16:13:53 +00:00 |
|
|
whitequark
|
790eb05a92
|
Rename fhdl→hdl, genlib→lib.
|
2018-12-15 14:25:31 +00:00 |
|
|
whitequark
|
b70340c0da
|
pyback.sim: test Slice, Cat, Repl.
|
2018-12-15 10:09:14 +00:00 |
|
|
whitequark
|
db4600d52b
|
fhdl.ast, back.pysim: implement shifts.
|
2018-12-15 09:58:30 +00:00 |
|
|
whitequark
|
46f5addf05
|
fhdl.ast: refactor Operator.shape(). NFC.
|
2018-12-15 09:46:20 +00:00 |
|
|
whitequark
|
f9f7921959
|
fhdl.ir: test iter_comb(), iter_sync() and iter_signals().
|
2018-12-15 09:26:36 +00:00 |
|
|
whitequark
|
f5e8c9033d
|
fhdl.ir: fix incorrect uses of positive to say non-negative.
Also test Part and Slice properly.
|
2018-12-15 09:26:23 +00:00 |
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|
whitequark
|
2001359b66
|
fhdl.ir: automatically flatten hierarchy to resolve driver conflicts.
Fixes #5.
|
2018-12-14 22:48:17 +00:00 |
|
|
whitequark
|
579feaba4e
|
fhdl.ir: Fragment.{drive→add_driver}
|
2018-12-14 20:58:29 +00:00 |
|
|
whitequark
|
50ba443f92
|
fhdl.ast: fix Switch with constant test.
|
2018-12-14 16:09:51 +00:00 |
|
|
whitequark
|
9307a31678
|
back.pysim: Simulator({gtkw_signals→traces}=).
|
2018-12-14 15:23:22 +00:00 |
|
|
whitequark
|
474d46ced8
|
back.pysim: implement most operators and add tests.
|
2018-12-14 14:21:22 +00:00 |
|
|
whitequark
|
7d91dd56c8
|
fhdl.xfrm: implement DomainLowerer.
|
2018-12-14 10:56:53 +00:00 |
|
|
whitequark
|
fb27c2520b
|
back.pysim: new simulator backend (WIP).
|
2018-12-13 18:02:46 +00:00 |
|
|
whitequark
|
71f1f717c4
|
fhdl.cd: rename ClockDomain signals together with domain.
|
2018-12-13 15:24:55 +00:00 |
|
|
whitequark
|
07c818e077
|
fhdl.ir: move Fragment prepare logic from back.rtlil.
|
2018-12-13 14:34:07 +00:00 |
|
|
whitequark
|
90f1503c91
|
fhdl.ir: record port direction explicitly.
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
|
2018-12-13 13:12:31 +00:00 |
|
|
whitequark
|
9661e897e6
|
fhdl.ir: a subfragment's input that we don't drive is also our input.
|
2018-12-13 11:50:56 +00:00 |
|
|
whitequark
|
b150f1915d
|
fhdl.ir: don't crash propagataing ports in empty fragments.
|
2018-12-13 11:25:49 +00:00 |
|
|
whitequark
|
72257b6935
|
fhdl.ir: implement clock domain propagation.
|
2018-12-13 11:01:03 +00:00 |
|
|
whitequark
|
c5087edfa5
|
fhdl.cd: add tests.
|
2018-12-13 09:19:16 +00:00 |
|
|
whitequark
|
9bee90f1bd
|
fhdl.xfrm: implement DomainRenamer.
|
2018-12-13 08:57:14 +00:00 |
|
|
whitequark
|
8963ab5d9f
|
fhdl.xfrm: add test for ControlInserter with subfragments.
|
2018-12-13 08:45:10 +00:00 |
|
|
whitequark
|
19aa404628
|
fhdl.xfrm: add tests for ResetInserter, CEInserter.
|
2018-12-13 08:39:02 +00:00 |
|
|
whitequark
|
b1a89ef5fd
|
fhdl.ir: add tests for port propagation.
|
2018-12-13 08:09:39 +00:00 |
|
|
whitequark
|
a797e27573
|
fhdl.dsl: add tests for lowering. 99% branch coverage.
|
2018-12-13 07:33:59 +00:00 |
|
|
whitequark
|
e0a81edf4d
|
fhdl.dsl: add tests for submodules.
|
2018-12-13 07:24:28 +00:00 |
|
|
whitequark
|
932f1912a2
|
fhdl.dsl: use less error-prone Switch/Case two-level syntax.
|
2018-12-13 07:11:06 +00:00 |
|
|
whitequark
|
f70ae3bac5
|
fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
|
2018-12-13 06:06:51 +00:00 |
|
|
whitequark
|
f0f4c0ce61
|
fhdl.ast: bits_sign→shape.
|
2018-12-13 02:06:58 +00:00 |
|
|
whitequark
|
dc486ad8b9
|
fhdl.ast: add tests for most logic.
|
2018-12-13 02:06:55 +00:00 |
|