whitequark
198efcad31
hdl.xfrm: add SampleLowerer.
2019-01-17 01:41:02 +00:00
whitequark
b3de114d67
hdl.ast: add Sample.
2019-01-17 01:36:27 +00:00
whitequark
b78a2be9f6
lib.fifo: port sync FIFO queues from Migen.
2019-01-16 17:20:38 +00:00
whitequark
cb2f18ee37
hdl.ast: fix naming of Signal.like() signals when tracer fails.
2019-01-16 17:20:38 +00:00
whitequark
f2425001aa
back.rtlil: slightly nicer naming for $next signals. NFC.
2019-01-16 17:20:38 +00:00
whitequark
935bf2d8cf
back.rtlil: rename \sig$next to $next$sig.
...
These used to serve a useful purpose being public, back when the RTLIL
backend was immature. Not anymore; now they merely clutter up views
in gtkwave and so on.
2019-01-16 14:51:20 +00:00
whitequark
6191760c30
Unbreak 655d02d5.
2019-01-15 23:09:10 +00:00
William D. Jones
655d02d5b8
back.rtlil: Generate $anyconst and $anyseq cells.
2019-01-15 22:52:45 +00:00
William D. Jones
77728c2dea
hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children.
2019-01-15 22:52:45 +00:00
William D. Jones
6fdbc3d885
hdl.ast: Add AnyConst and AnySeq value types.
2019-01-15 22:52:45 +00:00
whitequark
c4276f7cf7
lib.io: pass pin to platform.get_tristate().
2019-01-14 21:39:19 +00:00
whitequark
b534e92dd5
hdl.ir: allow explicitly requesting flattening.
2019-01-14 17:04:23 +00:00
whitequark
6f66885c09
lib.io: lower to platform-independent tristate buffer.
2019-01-14 16:50:04 +00:00
whitequark
011bf2258e
hdl: make ClockSignal and ResetSignal usable on LHS.
...
Fixes #8 .
2019-01-14 15:38:16 +00:00
whitequark
664b4bcb3a
hdl.dsl: cases wider than switch test value are unreachable.
...
In 3083c1d6
2019-01-13 08:51:49 +00:00
whitequark
3083c1d6dd
hdl.dsl: accept (but warn on) cases wider than switch test value.
...
Fixes #13 .
2019-01-13 08:46:28 +00:00
whitequark
cbf7bd6e31
back.pysim: handle non-driven, non-port signals.
...
Fixes #20 .
2019-01-13 08:31:38 +00:00
whitequark
06faeee357
back.verilog: better error message if Yosys is not found.
...
Fixes #17 .
2019-01-13 08:10:23 +00:00
whitequark
307de722cb
back.verilog: remove undriven check.
...
This check no longer finds bugs and is prone to false positives.
Instead, we should do integration tests on the entire stack, from
fragments to Verilog.
Fixes #23 .
2019-01-08 22:43:09 +00:00
Adam Greig
560bb007cc
Give the top level scope a name to fix VCD hierarchy.
2019-01-06 00:10:37 +00:00
whitequark
a2b04d71d0
hdl.ast: allow slicing [n:n] into n-bit value.
2019-01-02 18:14:57 +00:00
whitequark
ef1e0b8d55
back.rtlil: translate empty slices correctly.
2019-01-02 18:14:29 +00:00
William D. Jones
f31055a4ef
back.rtlil: Generate RTLIL for Assert/Assume statements.
2019-01-02 11:17:39 +00:00
William D. Jones
f77dc40256
hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children.
2019-01-02 11:17:39 +00:00
William D. Jones
2412650f56
hdl.dsl: Support Assert and Assume where an Assign can occur.
2019-01-02 11:17:39 +00:00
William D. Jones
e6517a33c7
hdl.ast: Add Assert and Assign statements.
2019-01-02 11:17:39 +00:00
whitequark
ea7e19ed5c
hdl.ast: experimentally add Value._as_const.
...
Useful for writing e.g. decoders that accept Cat, etc as argument.
2019-01-01 09:50:39 +00:00
whitequark
1a9dcd2f28
back.rtlil: fix typo.
2019-01-01 08:50:28 +00:00
whitequark
3c07d8d52c
hdl.rec: include record name in error message.
2019-01-01 03:39:12 +00:00
whitequark
031a9e2616
hdl.rec: use a helpful error on unknown field reference.
2019-01-01 03:35:34 +00:00
whitequark
d78e6c155b
hdl.mem: add DummyPort, for testing and verification.
2019-01-01 03:08:10 +00:00
whitequark
ae3c5834ed
back.rtlil: match shape of Array elements to ArrayProxy shape.
...
Fixes #15 .
2018-12-31 03:43:34 +00:00
whitequark
cdc40eaa9b
back.rtlil: fix typo.
2018-12-31 03:37:38 +00:00
whitequark
39eb2e8fa7
lib.cdc: fix tests to actually run.
2018-12-29 15:02:44 +00:00
whitequark
849c649259
back.pysim: warn if simulation is not run.
...
This would have prevented 3ea35b85
2018-12-29 15:02:04 +00:00
whitequark
92a96e1644
hdl.rec: add basic record support.
2018-12-28 13:22:10 +00:00
whitequark
d66bbb0df8
tracer: factor out get_src_loc().
2018-12-28 01:31:24 +00:00
whitequark
3ea35b8566
lib.coding: fix tests to actually run, and fix code to fix tests.
2018-12-27 21:45:55 +00:00
whitequark
470d66934f
hdl.dsl: add support for fsm.ongoing().
2018-12-27 16:19:01 +00:00
whitequark
de50ccec90
hdl.mem: add missing __all__.
2018-12-27 16:19:01 +00:00
Jean-François Nguyen
73ed870309
compat.genlib.coding: fix import.
2018-12-26 14:30:01 +00:00
whitequark
528747703d
lib.coding: port from Migen.
2018-12-26 13:19:34 +00:00
whitequark
fe8cb55204
lib.cdc: add tests for MultiReg.
2018-12-26 12:58:30 +00:00
whitequark
35a44f017f
hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.
2018-12-26 12:42:43 +00:00
whitequark
934546e633
hdl.dsl: provide generated values for FSMs.
2018-12-26 12:39:05 +00:00
whitequark
040811c2e5
hdl.ir: add an API for retrieving generated values, like FSM signal.
...
This is useful for tests.
2018-12-26 12:35:35 +00:00
whitequark
597d778cf6
examples: add an FSM usage example (UART receiver).
2018-12-26 10:10:27 +00:00
whitequark
72039b6072
hdl.dsl: add signal decoder to FSM state signal.
2018-12-26 09:45:12 +00:00
whitequark
54e3195dcb
hdl.dsl: implement FSM.
2018-12-26 08:55:04 +00:00
whitequark
b4fbef65ca
back.rtlil: clarify $verilog_initial_trigger behavior. NFC.
2018-12-26 06:45:57 +00:00
whitequark
010ddb96b5
back.rtlil: unbreak d47c1f8a.
2018-12-24 19:11:07 +00:00
whitequark
f05bd2a137
hdl.mem: allow omitting memory simulation logic.
...
Trying to transform very large arrays is slow.
2018-12-24 11:53:59 +00:00
whitequark
d47c1f8a8a
back.rtlil: use one $meminit cell, not one per word.
...
This is *far* more efficient.
2018-12-24 11:53:58 +00:00
whitequark
98f554aa08
hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
...
This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.
2018-12-24 02:17:28 +00:00
whitequark
1c7c75a254
hdl.xfrm: implement SwitchCleaner, for pruning empty switches.
2018-12-24 02:02:59 +00:00
whitequark
fc0fb9d89f
back.rtlil: always output negative values as two's complement.
...
- is valid in RTLIL but means something entirely different.
2018-12-24 01:38:32 +00:00
whitequark
5702767263
back.rtlil: emit dummy logic to work around Verilog deficiencies.
2018-12-23 10:14:42 +00:00
whitequark
9faa1d3742
back.rtlil: do not translate empty fragments.
...
The resulting Verilog confuses some frontends.
2018-12-23 09:20:02 +00:00
whitequark
45a474788c
back.rtlil: only translate switch tests once.
...
This seems to affect synthesis with Yosys but only marginally.
It is mostly a speed and readability improvement.
2018-12-23 07:17:52 +00:00
whitequark
4e49772f67
cli: generate: guess file type from extension.
2018-12-23 07:13:17 +00:00
whitequark
2b6ddbb713
back.rtlil: fix swapped operands in mux codegen.
2018-12-23 06:47:38 +00:00
whitequark
cf79738744
cli: new module, for basic design generaton/simulation.
2018-12-23 00:06:58 +00:00
whitequark
621dddebfd
hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
2018-12-22 22:19:14 +00:00
whitequark
3448953f61
compat.genlib.fsm: fix naming for non-Signal LHS.
2018-12-22 22:00:58 +00:00
whitequark
68dae9f50e
hdl.ir: flatten hierarchy based on memory accesses, too.
2018-12-22 21:43:46 +00:00
whitequark
fd89d2fc9d
hdl.ir: factor out _merge_subfragment. NFC.
2018-12-22 19:04:49 +00:00
whitequark
59c7540aeb
back.rtlil: split processes as finely as possible.
...
This makes simulation work correctly (by introducing delta cycles,
and therefore, making the overall Verilog simulation deterministic)
at the price of pessimizing mux trees generated by Yosys and Synplify
frontends, sometimes severely.
2018-12-22 10:03:16 +00:00
whitequark
d29929912f
back.rtlil: remove useless condition. NFC.
2018-12-22 07:24:15 +00:00
whitequark
ae0cb48fbb
hdl.xfrm: implement LHSGroupAnalyzer.
2018-12-22 06:58:24 +00:00
whitequark
98a9744be4
hdl.xfrm: Abstract*Transformer→*Visitor
2018-12-22 06:03:39 +00:00
whitequark
37b81309d3
back.rtlil: always initialize the entire memory.
...
This avoids reading 'x from the memory in simulation. In general,
FPGA memories can only be initialized in block granularity, and
zero-initializing is cheap, so this is not a significant issue with
resource consumption.
2018-12-22 05:27:42 +00:00
whitequark
99b778158d
compat: use nicer names for next_value/next_value_ce signals.
2018-12-22 02:05:49 +00:00
whitequark
8730895d8c
hdl.mem: allow changing init value after creating memory.
2018-12-22 01:09:03 +00:00
whitequark
6ee80408bb
back.verilog: do not rename internal signals.
...
_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
2018-12-22 00:53:40 +00:00
whitequark
5361b4c22b
compat: fix confusing naming for memory port address signal.
2018-12-22 00:53:05 +00:00
whitequark
f6772759c8
hdl.ir: fix port propagation between siblings, in the other direction.
2018-12-22 00:31:31 +00:00
whitequark
0df543b204
compat: do not finalize native submodules twice.
2018-12-22 00:02:31 +00:00
whitequark
a4183eba69
hdl.mem: use more informative signal naming for ports.
2018-12-21 23:55:02 +00:00
whitequark
913339c04a
hdl.ir: fix port propagation between siblings.
2018-12-21 23:53:18 +00:00
whitequark
00ef7a78d3
compat: provide verilog.convert shim.
2018-12-21 13:53:06 +00:00
whitequark
fc7da1be2d
hdl.ir: do not flatten instances or collect ports from their statements.
...
This results in absurd behavior for memories.
2018-12-21 13:52:18 +00:00
whitequark
568d3c5b7d
compat: provide Memory shim.
2018-12-21 13:15:52 +00:00
whitequark
fa2af27bb0
hdl.mem: ensure transparent read port model has correct latency.
2018-12-21 13:01:08 +00:00
whitequark
48d13e47ec
back.pysim: handle out of bounds ArrayProxy indexes.
2018-12-21 12:32:08 +00:00
whitequark
7ae7683fed
back.pysim: give numeric names to unnamed subfragments in VCD.
2018-12-21 12:29:33 +00:00
whitequark
af7db882c0
hdl.mem: use different naming for array signals.
...
It looks like [] is confusing gtkwave somehow.
2018-12-21 12:26:49 +00:00
whitequark
e58d9ec74d
hdl.mem: add simulation model for memory.
2018-12-21 11:54:32 +00:00
whitequark
a40e2cac4b
back.pysim: fix an issue with too few funclet slots.
2018-12-21 10:25:28 +00:00
whitequark
c49211c76a
hdl.mem: add tests for all error conditions.
2018-12-21 06:07:16 +00:00
whitequark
a061bfaa6c
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
2018-12-21 04:22:16 +00:00
whitequark
8d58cbf230
back.rtlil: more consistent prefixing for subfragment port wires.
2018-12-21 04:21:11 +00:00
whitequark
b0bd7bfaca
hdl.ir: correctly handle named output and inout ports.
2018-12-21 04:03:03 +00:00
whitequark
2b4a8510ca
back.rtlil: implement memories.
2018-12-21 01:55:59 +00:00
whitequark
6d9a6b5d84
hdl.mem: implement memories.
2018-12-21 01:53:32 +00:00
whitequark
6672ab2e3f
back.rtlil: explicitly pad constants with zeroes.
...
I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.
2018-12-21 01:51:18 +00:00
whitequark
221f108fbe
back.rtlil: fix translation of Cat.
2018-12-21 01:48:02 +00:00
whitequark
f7fec804ec
ir: allow non-Signals in Instance ports.
2018-12-20 23:40:40 +00:00
whitequark
0f2c7e7161
compat: import genlib.record from Migen.
2018-12-18 20:04:22 +00:00
whitequark
a90748303c
compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.
2018-12-18 20:03:32 +00:00
whitequark
dbbcc49a71
hdl.ast: Cat.{operands→parts}
2018-12-18 19:15:50 +00:00
whitequark
4199674edd
back.pysim: implement *.
2018-12-18 18:02:21 +00:00
whitequark
07e9cfa939
test.sim: add tests for sync functionality and errors.
2018-12-18 17:53:50 +00:00
whitequark
7fa82a70be
back.pysim: eliminate most dictionary lookups.
...
This makes the Glasgow testsuite about 30% faster.
2018-12-18 16:36:54 +00:00
whitequark
7341d0d7ef
hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim.
2018-12-18 16:13:29 +00:00
whitequark
c5f169988b
back.pysim: use arrays instead of dicts for signal values.
...
This makes the Glasgow testsuite about 40% faster.
2018-12-18 05:20:20 +00:00
whitequark
39605ef551
back.pysim: naming. NFC.
2018-12-18 04:46:36 +00:00
whitequark
65702719e8
back.pysim: fix an off-by-1 in add_sync_process().
2018-12-18 04:43:04 +00:00
whitequark
34b81d0b87
back.pysim: trigger processes waiting on Tick() exactly at clock edge.
2018-12-18 04:37:39 +00:00
whitequark
d6e98fd934
back.pysim: continue running simulator processes until they suspend.
2018-12-18 03:05:16 +00:00
whitequark
c7f9386eab
fhdl.ir: add black-box fragments, fragment parameters, and Instance.
2018-12-17 22:55:39 +00:00
whitequark
8d1639a5a8
hdl, back: add and use SignalSet/SignalDict.
2018-12-17 17:21:29 +00:00
whitequark
8c4de99c0d
hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.
2018-12-17 17:21:29 +00:00
whitequark
f1e390cbc9
back.rtlil: update for Yosys master.
2018-12-17 15:50:43 +00:00
whitequark
850674637a
back.rtlil: implement Array.
2018-12-17 01:15:23 +00:00
whitequark
87cd045ac3
back.rtlil: implement Part.
2018-12-17 01:05:08 +00:00
whitequark
f968678937
back.rtlil: handle reset_less domains.
2018-12-16 23:52:47 +00:00
whitequark
015998eba9
hdl.dsl: add clock domain support.
2018-12-16 23:51:24 +00:00
whitequark
b2f828387a
hdl.dsl: cleanup. NFC.
2018-12-16 23:44:00 +00:00
whitequark
91b7561a00
back.rtlil: extract _StatementCompiler. NFC.
2018-12-16 22:26:58 +00:00
whitequark
b9a0af8bde
back.rtlil: simplify. NFC.
2018-12-16 21:00:00 +00:00
whitequark
635094350f
back.rtlil: properly escape strings in attributes.
2018-12-16 20:27:36 +00:00
whitequark
33f32a25f5
back.rtlil: prepare for Yosys sigspec slicing improvements.
...
See YosysHQ/yosys#741 .
2018-12-16 18:03:14 +00:00
whitequark
db5fd1e4c4
compat.fhdl.structure: only convert to bool in If/Elif if necessary.
2018-12-16 17:41:42 +00:00
whitequark
9bce35098f
back.rtlil: avoid illegal slices.
...
Not sure what to do with {} [] on LHS yet--fix Yosys?
2018-12-16 17:41:11 +00:00
whitequark
e86104d3a6
back.rtlil: use slicing to match shape when reducing width.
2018-12-16 16:20:45 +00:00
whitequark
2833b36c73
back.rtlil: don't emit a slice if all bits are used.
2018-12-16 16:05:38 +00:00
whitequark
9794e732e2
back.rtlil: reorganize value compiler into LHS/RHS.
...
This also implements Cat on LHS.
2018-12-16 13:33:34 +00:00
whitequark
ed39748889
back.rtlil: fix naming. NFC.
2018-12-16 11:26:31 +00:00
whitequark
2be76fda3c
hdl.xfrm: separate AST traversal from AST identity mapping.
...
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
2018-12-16 11:25:52 +00:00
whitequark
286a8009c8
compat.fhdl: reexport Array.
2018-12-16 10:39:54 +00:00
whitequark
d4e8d3e95a
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
2018-12-16 10:31:42 +00:00
whitequark
d9579219ee
test.sim: generalize assertOperator. NFC.
2018-12-15 21:08:29 +00:00
whitequark
bdb8db2826
back.pysim: add (stub) LHSValueCompiler.
2018-12-15 21:01:38 +00:00
whitequark
20a04bca88
back.pysim: implement Part.
2018-12-15 20:58:06 +00:00
whitequark
54fb999c99
back.pysim: implement ArrayProxy.
2018-12-15 19:37:36 +00:00
whitequark
80c5343600
hdl.ast: implement Array and ArrayProxy.
2018-12-15 17:16:31 +00:00
whitequark
c6e7a93717
hdl: appropriately rename tests. NFC.
2018-12-15 16:13:53 +00:00
whitequark
f603b735e8
hdl.ast: improve ClockSignal, ResetSignal documentation.
2018-12-15 14:58:31 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
whitequark
b5a1efa0c8
Move star imports to make from nmigen import * usable.
2018-12-15 14:20:10 +00:00
whitequark
1f10bd96b9
Determine Migen's API surface and document compatibility summary.
...
This also reorganizes README to more clearly describe what nMigen is,
since it was getting quite outdated.
2018-12-15 11:52:30 +00:00
whitequark
b70340c0da
pyback.sim: test Slice, Cat, Repl.
2018-12-15 10:09:14 +00:00
whitequark
db4600d52b
fhdl.ast, back.pysim: implement shifts.
2018-12-15 09:58:30 +00:00
whitequark
46f5addf05
fhdl.ast: refactor Operator.shape(). NFC.
2018-12-15 09:46:20 +00:00
whitequark
3a8685c352
Consistently use '{!r}' in and only in TypeError messages.
2018-12-15 09:31:58 +00:00
whitequark
f9f7921959
fhdl.ir: test iter_comb(), iter_sync() and iter_signals().
2018-12-15 09:26:36 +00:00
whitequark
f5e8c9033d
fhdl.ir: fix incorrect uses of positive to say non-negative.
...
Also test Part and Slice properly.
2018-12-15 09:26:23 +00:00
whitequark
9010805040
compat.fhdl.structure: handle If/Elif with multi-bit condition.
2018-12-15 00:10:54 +00:00
whitequark
ecea721f43
compat.fhdl.module: allow adding native submodules to compat modules.
2018-12-14 23:56:50 +00:00
whitequark
1c7b43ea49
Fix deprecations in Python 3.7.
2018-12-14 23:56:50 +00:00
