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Author SHA1 Message Date
Catherine 3a8cd63b23 docs: cover amaranth.lib.coding. 2021-12-13 05:48:31 +00:00
Catherine 25163364d8 README: point IRC link to web.libera.chat. 2021-12-13 02:19:04 +00:00
Irides 0b74d1c5f6 back.rtlil: support slicing on Parts 
Fixes #605.
 2021-12-11 16:44:29 +00:00
whitequark 7c161957bf build.dsl: check type of resource number. 
Fixes #599.
 2021-12-11 13:37:15 +00:00
whitequark 7e2b72826f sim.core: warn when driving a clock domain not in the simulation. 
Closes #566.
 2021-12-11 13:22:24 +00:00
whitequark ac13a5b3c9 sim._pyrtl: reject very large values. 
A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.
 2021-12-11 13:00:46 +00:00
whitequark 599615ee3a hdl.ir: reject elaboratables that elaborate to themselves. 
Fixes #592.
 2021-12-11 12:40:05 +00:00
whitequark 90777a65c8 build.plat,vendor: add missing compatibility shims for NMIGEN_ENV_*. 
These have been mistakenly omitted from commit 909a3b8b.
 2021-12-11 12:40:05 +00:00
Irides b1eba5fd82 vendor.xilinx: support setting options on synth_design 
Closes #606.
 2021-12-11 12:09:09 +00:00
whitequark fd7d01ef10 back.rtlil,cli: allow suppressing generation of src attributes. 
Fixes #572.
 2021-12-11 11:38:40 +00:00
whitequark 66295fa388 sim.pysim: refuse to write VCD files with whitespace in signal names. 
Closes #595.
 2021-12-11 11:12:25 +00:00
whitequark b452e0e871 hdl.ast: support division and modulo with negative divisor. 
Fixes #621.

This commit bumps the Yosys version requirement to >=0.10.
 2021-12-11 10:25:48 +00:00
whitequark 25573c5eff back.rtlil: extend unsigned operand of binop if another is signed. 
Fixes #580.
 2021-12-11 10:25:48 +00:00
whitequark 44b8bd29af hdl.ast: warn on bare integer value used in Cat()/Repl(). 
Fixes #639.
 2021-12-11 08:18:33 +00:00
whitequark de7c9acb19 _utils: don't crash trying to flatten() strings. 
Fixes #614.
 2021-12-11 07:39:35 +00:00
whitequark 0fb2b4cd39 docs: fix download link in start.rst. 
Fixes #647.
 2021-12-11 06:32:32 +00:00
whitequark 116d4b9bc2 nmigen.cli: add missing imports. 2021-12-10 17:16:32 +00:00
whitequark 4d83e13103 CI: fix test discovery command. 2021-12-10 10:48:14 +00:00
whitequark a7fdf661cf CI: only discover tests under tests/. 
This avoids a crash importing the deprecated `nmigen` module with
PYTHONWARNINGS=error set.
 2021-12-10 10:45:05 +00:00
whitequark e11d033b0f README: update header. 2021-12-10 10:42:15 +00:00
whitequark 909a3b8be7 Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
whitequark 0b28a97ca0 CI: preserve YoWASP cache as well. 2021-11-05 19:08:21 +00:00
whitequark e91a5ad934 _toolchain.cxx: ignore another deprecation warning (on Python 3.10). 
Sigh.
 2021-11-05 19:03:46 +00:00
whitequark 3379f072a0 _toolchain.cxx: ignore deprecation warning (on Python 3.6). 
This code really shouldn't be using distutils, but for now this will
have to do.
 2021-11-05 18:58:26 +00:00
whitequark 369cc59d69 docs: update requirements. 
Sphinx 4.2 or later is required for compatibility with Python 3.10.

A released version of Pygments can now be used for highlighting.
 2021-11-05 18:53:09 +00:00
whitequark 8081df1265 _toolchain.cxx: use distutils from setuptools. 
The distutils module from the standard library is deprecated and will
be removed in Python 3.12, and PEP 632 recommends using
distutils.ccompiler from setuptools, instead.

This code should eventually be rewritten to use zig-pypi, but for now
this suffices.
 2021-11-05 18:48:50 +00:00
whitequark 97aa7a3aa9 vendor.xilinx_*: deprecate legacy Xilinx platform aliases. 2021-11-05 18:43:27 +00:00
whitequark f0af0a8449 Run tests on Python 3.10. 2021-11-05 18:40:45 +00:00
whitequark 7c740a85ea Simplify CI workflow. 2021-11-05 18:37:51 +00:00
whitequark a2ef4cb6b8 Add PEP 518 pyproject.toml. 2021-11-05 14:44:31 +00:00
Olivier Galibert 177f1b2e40
vendor.intel: add Mistral toolchain support. 2021-10-14 16:02:22 +00:00
whitequark 11914a1e67 hdl.ast: improve interaction of ValueCastable with custom __getattr__. 
Avoid calling `__getattr__("_ValueCastable__lowered_to")` when
a ValueCastable has custom `__getattr__` implementation; this avoids
the need for downstream code to be aware of this implementataion
detail.
 2021-10-03 20:28:07 +00:00
whitequark fac1b4b2d1 hdl.dsl: simplify. NFC. 2021-10-02 17:00:01 +00:00
whitequark e88d283ed3 hdl.ast: simplify Mux implementation. 2021-10-02 14:18:02 +00:00
whitequark 65499d5c45 hdl.ast: add tests for casting bare integers in {Cat,Repl}. 2021-10-02 13:18:11 +00:00
Anton Blanchard 9f78ac0691
hdl.ast: remove quadratic time complexity in Statement.cast(). 
Using `sum(lst, [])` to flatten a list of lists has quadratic time
complexity. Use `chain.from_iterable()` instead. While not strictly
necessary to improve performance, convert to `map()`.

A test case writing out verilog for a 512k entry FIFO is 120x faster
with this applied.
 2021-09-27 01:00:56 +00:00
H-S-S-11 9834b7e95f
vendor.xilinx: avoid using / for hierarchy in ISE constraint files. 2021-09-25 10:41:23 +00:00
Marcelina Kościelnicka bdbe8bff27 Unify Xilinx platforms into a single class, support more devices 
This merges existing code, and also adds support for:

- Virtex, Virtex E (also known as Spartan 2, Spartan 2E)
- Virtex 2, Virtex 2 Pro
- Spartan 3, Spartan 3E (in addition to existing Spartan 3A, Spartan 3A
  DSP support)
- Virtex 4
- Virtex 5
- Virtex 6
- ISE synthesis for Series 7

Fixes #552.
 2021-09-25 05:04:06 +00:00
Adam Jeliński da8a492be7 _toolchain: Properly set compiler/linker executables on Gentoo 
The `test_toolchain_cxx.py` tests on Gentoo definitely use compiler and
linker set with `_so_cxx`-suffixed executables. Tests use a proper
executable instead of `c++` after this change.

Signed-off-by: Adam Jeliński <ajelinski@antmicro.com>
 2021-09-25 03:35:10 +00:00
Robin Ole Heinemann 23a44f3cb6 vendor.xilinx_{7series,ultrascale}: hierachical -> hierarchical 
Signed-off-by: Robin Ole Heinemann <robin.ole.heinemann@gmail.com>
 2021-08-16 22:17:27 +00:00
Jean-François Nguyen abb2642256 _toolchain: substitute '+' with 'X' in tool_env_var(). 2021-07-17 06:27:44 +00:00
whitequark e974a31022
README: update IRC channel. 2021-05-20 03:07:51 +00:00
Robin Ole Heinemann 78be9e7b67 rpc: fix parsing of negative signed parameters 2021-05-18 20:54:40 +00:00
Robin Ole Heinemann b38b2cdad7 test.test_hdl_ast.OperatorTestCase: remove duplicate test_bool 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann 2d85f888d6 tests: rename tests with duplicate names 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann b93a54ac58 tests.test_hdl_cd.ClockDomainTestCase.test_name: actually test domain with cd_ prefix 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann f570e1bbeb *: remove unused variables 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann 25caf4045b *: remove unused imports 2021-05-18 20:18:55 +00:00
Thomas Watson d09dedfb48 tests.hdl.dsl: add tests for mis-nested Switch/Case and FSM/State statements 2021-05-11 02:41:32 +00:00
Thomas Watson 7443f89200 hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements 2021-05-11 02:41:32 +00:00