Commit graph

793 commits

Author SHA1 Message Date
whitequark fb90043460 lib.io: use keyword-only arguments in Pin(). 2019-10-16 19:50:04 +00:00
whitequark 045f5e19a2 setup: fix commit 5198d99b. 2019-10-16 14:57:40 +00:00
Sebastien Bourdeauducq 07b3510218 verilog: fix yosys version error message 2019-10-16 13:10:19 +08:00
whitequark 58300d8eb6 back.verilog: fix Yosys version check. 2019-10-16 02:25:35 +00:00
whitequark 5198d99b5e setup: don't append local version for tags.
PyPI rejects any archives with local version.
2019-10-15 04:05:13 +00:00
whitequark 1bb3fa861c vendor.lattice_ice40: fix commit 88649def. 2019-10-14 15:55:11 +00:00
whitequark b3a8a43152 vendor.lattice_{ice40,ecp5}: fix typo. 2019-10-13 22:17:46 +00:00
whitequark 88649defda vendor.lattice_ice40: use pcf files instead of pre-pack Python scripts.
This allows to use nextpnr-ice40 built without Python with nMigen.
Requires nextpnr revision
YosysHQ/nextpnr@8c0610e84f or newer.
2019-10-13 21:56:40 +00:00
whitequark be6c16d0a2 build.plat: batch files use EQU, not EQ. 2019-10-13 21:45:56 +00:00
whitequark 2f9dab361f {,_}tools→{,_}utils
In context of nMigen, "tools" means "parts of toolchain", so it is
confusing to have a completely unrelated module also called "tools".
2019-10-13 18:53:38 +00:00
whitequark ccd28b40c2 vendor.lattice_{ice40,ecp5}: emit Verilog as well, for debugging. 2019-10-13 18:04:33 +00:00
whitequark b8b8e0ba0b build.plat: fold emit_prelude() into emit_commands().
Commit a783e464 broke all toolchains using bash.
2019-10-13 13:57:48 +00:00
Emily a783e4645d Refactor build script toolchain lookups.
Now environment variable overrides no longer infect the build scripts.

_toolchain.overrides is dropped as probably misguided in the first place.

Fixes #251.
2019-10-13 13:53:24 +00:00
whitequark 29253295ee hdl.ir: allow ClockSignal and ResetSignal in ports.
Fixes #248.
2019-10-13 03:39:56 +00:00
whitequark 722b3879f4 hdl.ir: cast instance port connections to Values.
Fixes #249.
2019-10-13 03:19:17 +00:00
whitequark 13650acbbc compat.fhdl.decorators: improve backwards compatibility. 2019-10-13 01:38:09 +00:00
whitequark d2c4c7c060 compat.fhdl.bitcontainer: update Value.wrap call. 2019-10-13 01:37:11 +00:00
whitequark 1334bd6a8b doc: bring COMPAT_SUMMARY up to date.
Fixes #112.
2019-10-12 23:15:09 +00:00
whitequark 1387e2f9df compat.genlib.fsm: add migration warning. 2019-10-12 22:48:08 +00:00
whitequark dbddddff17 compat.fhdl.decorators: add migration warnings. 2019-10-12 22:45:03 +00:00
whitequark a7e3b80409 hdl.ast: rename Slice.end back to Slice.stop.
It used to be called .stop in oMigen, and it's also called .stop in
Python range and slice objects, so keep that.
2019-10-12 22:40:48 +00:00
whitequark 77118fb9c9 compat.fhdl.structure: remove SPECIAL_* constants.
They cannot be used with nMigen designs since nMigen does not have
specials.
2019-10-12 22:40:48 +00:00
whitequark da48c05bdf _tools: extract most utility methods to a private package.
We don't want to guarantee backwards compatibility for most of them.
2019-10-12 22:40:48 +00:00
Jean-François Nguyen a97003d57a back.rtlil: fix DeprecationWarning. NFC. 2019-10-12 21:50:40 +00:00
whitequark b90687c988 Rename remaining wrap methods to cast.
Following commit d72d4a55.
2019-10-11 13:28:26 +00:00
whitequark a658cb2bbf hdl.ast: deprecate shapes like (1, True) in favor of signed(1).
This is a great improvement in clarity.
2019-10-11 13:22:08 +00:00
whitequark 706bfaf5e1 hdl.ast: deprecate Signal.{range,enum}.
Although constructor methods can improve clarity, there are many
contexts in which it is useful to use range() as a shape: notably
Layout, but also Const and AnyConst/AnyValue. Instead of duplicating
these constructor methods everywhere (which is not even easily
possible for Layout), use casting to Shape, introduced in 6aabdc0a.

Fixes #225.
2019-10-11 13:07:42 +00:00
whitequark 6aabdc0a73 hdl.ast: add an explicit Shape class, included in prelude.
Shapes have long been a part of nMigen, but represented using tuples.
This commit adds a Shape class (using namedtuple for backwards
compatibility), and accepts anything castable to Shape (including
enums, ranges, etc) anywhere a tuple was accepted previously.

In addition, `signed(n)` and `unsigned(n)` are added as aliases for
`Shape(n, signed=True)` and `Shape(n, signed=False)`, transforming
code such as `Signal((8, True))` to `Signal(signed(8))`.
These aliases are also included in prelude.

Preparation for #225.
2019-10-11 12:52:41 +00:00
whitequark db960e7c30 Consistently use {!r}, not '{!r}' in diagnostics.
This can cause confusion:
  * If the erroneous object is None, it is printed as 'None', which
    appears as a string (and could be the result of converting None
    to a string.)
  * If the erroneous object is a string, it is printed as ''<val>'',
    which is a rather strange combination of quotes.
2019-10-11 11:47:42 +00:00
whitequark fa1e466a65 hdl.ast: Operator.{op→operator}
Both "operator" and "operand" were shortened to "op" in different
places in code, which caused confusion.
2019-10-11 11:37:26 +00:00
whitequark 7ff4c6ce43 hdl.ast: simplify enum handling. 2019-10-11 11:16:00 +00:00
whitequark d72d4a55fd hdl.ast: Value.{wrap→cast}
Preparation for #225.
2019-10-11 10:49:34 +00:00
whitequark 9fe27a15ad vendor.xilinx_ultrascale: new supported family. 2019-10-10 16:35:48 +00:00
whitequark bfd4538df0 xilinx_7series: add grade platform property.
For some devices grade has to be omitted, so it is optional.
2019-10-10 16:33:00 +00:00
whitequark ef741594b5 vendor.lattice_machxo2: new supported family. 2019-10-10 16:22:29 +00:00
whitequark a7cc88f3d4 vendor: yosys is a required tool for all Verilog-based flows. 2019-10-10 14:38:09 +00:00
whitequark 730eff5d57 README: add device support matrix. 2019-10-10 00:50:16 +00:00
whitequark 8021e2dd76 vendor.intel: add Quartus support.
Co-authored-by: Dan Ravensloft <dan.ravensloft@gmail.com>
2019-10-10 00:35:13 +00:00
whitequark 7dfd7fb12a examples: update blinky, add some explanatory text about domains. 2019-10-09 23:19:28 +00:00
whitequark 7257c20a6a build.plat: elaborate result of create_missing_domain() against platform.
Before this commit, the result was elaborated without platform, which
caused generic implementation of e.g. ResetSynchronizer to be used.
2019-10-09 21:16:20 +00:00
whitequark 27a32f0218 build.plat: don't create default sync domain as reset-less. 2019-10-09 20:44:07 +00:00
whitequark b9e57fd67b build.plat,vendor: always synchronize reset in default sync domain.
This change achieves two related goals.

First, default_rst is no longer assumed to be synchronous to
default_clk, which is  the safer option, since it can be connected to
e.g. buttons on some evaluation boards.

Second, since the power-on / configuration reset is inherently
asynchronous to any user clock, the default create_missing_domain()
behavior is to use a reset synchronizer with `0` as input. Since,
like all reset synchronizers, it uses Signal(reset=1) for its
synchronization stages, after power-on reset it keeps its subordinate
clock domain in reset, and releases it after fabric flops start
toggling.

The latter change is helpful to architectures that lack an end-of-
configuration signal, i.e. most of them. ECP5 was already using
a similar scheme (and is not changed here). Xilinx devices with EOS
use EOS to drive a BUFGMUX, which is more efficient than using
a global reset when the design does not need one; Xilinx devices
without EOS use the new scheme. iCE40 requires a post-configuration
timer because of BRAM silicon bug, and was changed to add a reset
synchronizer if user clock is provided.
2019-10-09 20:02:33 +00:00
whitequark 2512a9a12d back.rtlil: don't crash legalizing values with no branches.
Fixes #239.
2019-10-06 08:52:49 +00:00
whitequark 964c67453f back.rtlil: avoid unsoundness for division by zero.
Fixes #238.
2019-10-04 08:15:45 +00:00
whitequark de34728bf8 hdl.ast: prohibit signed divisors.
See #238.
2019-10-04 07:49:24 +00:00
whitequark 751ae33fe1 build.dsl: accept Pins(invert=True).
The PinsN() form is still preferred, but Pins(invert=) form is useful
for code generic over pin polarity.
2019-10-03 02:44:43 +00:00
whitequark 9458de2079 hdl.ast: don't crash on Mux(<bool>, ...).
Fixes #240.
2019-10-02 08:30:15 +00:00
whitequark d139f340b3 back.rtlil: don't cache wires for legalized switch tests.
This causes miscompilation of code such as:

  r = Array([self.a, self.b])
  m = Module()
  with m.If(r[self.s]):
      m.d.comb += self.o.eq(1)
  return m
2019-10-02 07:51:49 +00:00
whitequark d3f7cc8ed2 back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow} don't need to match. 2019-10-02 03:50:20 +00:00
whitequark 3a1dae591b back.rtlil: it is not necessary to match binop operand width. 2019-10-02 03:38:58 +00:00