Commit graph

390 commits

Author SHA1 Message Date
Wanda 598cf8db28 lib.io: Implement *Port from RFC 55. 2024-03-18 23:56:34 +00:00
Wanda 744576011f Implement RFC 53: Low-level I/O primitives.
Co-authored-by: Catherine <whitequark@whitequark.org>
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
2024-03-18 20:33:22 +00:00
Wanda 18b54ded0a hdl._ir: Fix fallout from #1190, add more tests. 2024-03-16 14:17:00 +00:00
Wanda 23f1b63425 lib.memory: Add Signature.create implementations. 2024-03-16 08:48:32 +00:00
Catherine 11ec35d258 lib.wiring: remove unnecessary flipping in Signature.flatten. 2024-03-15 10:35:50 +00:00
mcc 27ca96383e utils: F-strings are missing the letter "f"
Also adds tests for utils ValueError strings.
2024-03-13 14:56:27 +00:00
Wanda 5edff532a8 sim: Do not direct user to deprecated add_sync_process. 2024-03-13 13:12:34 +00:00
Wanda 455a7bc6c8 lib.memory: Allow setting Memory.init.
The `init` property is already mutable, so this adds no actual new
functionality, just convenience.
2024-03-13 13:12:15 +00:00
Wanda cb96b15b8c hdl._ir: Remove all support for fragment flattening. 2024-03-11 21:28:46 +00:00
Wanda bfe541a6d7 Implement RFC 50: Print and string formatting.
Co-authored-by: Catherine <whitequark@whitequark.org>
2024-03-11 09:42:43 +00:00
Jean-François Nguyen 715a8d4934 lib.memory: strip whitespace. 2024-03-08 15:47:21 +00:00
Wanda 161b01450e hdl._ast, hdl._ir: Deduplicate shape unification logic. NFC 2024-03-05 12:24:02 +00:00
Wanda 31a12c03d1 hdl._ir: Remove support for the nonexistent unary "+" operator. 2024-03-03 23:51:38 +00:00
Wanda c2001fe935 vendor: Rename IntelPlatform to AlteraPlatform.
Fixes #1179.
2024-03-03 22:52:58 +00:00
Wanda 127fe1fd2e hdl._xfrm: Get rid of _insert_resets, move the logic downstream. 2024-03-03 19:34:35 +00:00
Wanda ea561378ac hdl._nir: Remove ArrayMux, use AssignmentList instead. 2024-03-03 18:52:21 +00:00
Wanda fc9369b8e1 hdl._xfrm: Simplify EnableInserter logic. 2024-03-03 18:38:20 +00:00
Wanda 7d295b040a test_hdl_ir: Add a bunch of tests for NIR emitter. 2024-03-03 18:09:08 +00:00
Wanda 3ae7714d04 hdl._ir: Fix reset-less signals in async reset domains. 2024-03-03 18:09:08 +00:00
Wanda 2400d39730 lib.io: Make Pin.name return the whole path.
This prevents duplicate pin names.
2024-02-29 20:32:43 +00:00
Catherine 871d726ad4 build.plat: use tcl_quote instead of tcl_escape.
The premise of `tcl_escape` is incorrect: it is not possible, by design,
to escape a single backslash inside of a Tcl {}-quoted string:

    $ tclsh
    % puts {\\}
    \\

`tcl_quote` should be used instead since it can escape arbitrary strings
(and uses the right algorithm already).
2024-02-29 20:07:38 +00:00
Jaro Habiger 65191be1b1 vendor._lattice_{ice40,ecp5,machxo_2_3l}: fix SDC hierarchy separator. 2024-02-29 20:07:38 +00:00
Catherine 4399700273 vendor._lattice_machxo2_3l: fix buffer factories. 2024-02-29 20:07:38 +00:00
Wanda 76a7dc396c hdl._ir: Handle duplicate fragment names. 2024-02-29 20:03:38 +00:00
Wanda 2bf1b4dafc hdl._ast: Make AST nodes immutable.
Fixes #1067.
2024-02-29 18:56:46 +00:00
Wanda 3271f85650 hdl._nir: Add empty __slots__ to Net and Value. 2024-02-29 18:54:57 +00:00
Wanda f8e2d26b8f hdl._ir: Inline AssignmentLegalizer into netlist building.
Fixes #1150.
2024-02-28 15:15:42 +00:00
Wanda 544258354b build.plat, back.rtlil: Fix #1104 fallout. 2024-02-28 13:51:10 +00:00
Wanda 2356e8d06b build.plat: Fix toolchain_prepare interface breakage. 2024-02-28 12:23:38 +00:00
Wanda f2dab705ee lib.io: Expose Pin path and name as attributes. 2024-02-28 11:49:35 +00:00
Wanda 1dd2e6150c lib.io: Add missing __repr__ to signature type. 2024-02-28 09:11:53 +00:00
Wanda 8af9fe2606 lib.memory: Add missing __eq__ to signature types. 2024-02-28 09:06:49 +00:00
Wanda c6bc9b47ef hdl.ir: add IOBufferInstance. 2024-02-27 18:56:24 +00:00
Wanda 85bb5ee77c hdl._dsl: Change FSM codegen to avoid mutating AST nodes.
Fixes #1066.
2024-02-27 16:20:25 +00:00
Wanda f524dd041a lib.io, build.res: Make Pin and related objects interfaces.
Fixes #1040.
2024-02-27 11:40:25 +00:00
Wanda c30585b47b back.rtlil: Emit proper source location for port-signals. 2024-02-27 11:06:42 +00:00
Wanda 1cb9d43841 back.rtlil: Remove code allowing internal yosys cells in Instance.
This was allowed only because Amaranth used it internally. Now that
all uses are gone, let's just disallow it entirely.
2024-02-27 10:34:30 +00:00
Wanda 751e0f4b57 ir: kill Fragment.ports 2024-02-27 08:26:30 +00:00
Wanda a725282751 sim.pysim: Only close VCD/GTKW files if we opened them ourselves.
Fixes #1107.
2024-02-27 07:42:39 +00:00
Wanda fc81ff17f7 hdl._ir: Improve driver-driver conflict message. 2024-02-27 06:31:27 +00:00
Wanda ccf87c62e4 back.rtlil: strip \ from names added to name_map.
Fixes #1154.
2024-02-27 06:26:56 +00:00
Amelia Cuss a586df89ad lib.wiring.connect: diagnostic when no connection made.
If a connect() call results in no connections being made, and it's
because there were no outputs specified at all, issue an error.
Tests enumerate cases per
https://github.com/amaranth-lang/amaranth/pull/1153#issuecomment-1962810678.

Co-authored-by: Catherine <whitequark@whitequark.org>
2024-02-25 09:33:46 +00:00
Catherine 09029cdd91 hdl._ir: remember origins of a fragment during elaboration.
This isn't expected to result in a significant increase in memory use,
so for now it's enabled by default. Elaboration chains where it is not
desired to preserve origins can delete the `origins` attribute from
the fragment and nothing will be stored.

The interface `Fragment.origins` remains private, as is the rest of
the `Fragment` interface (including itself), but it enables certain
codebases that currently use a much more invasive technique to rely on
reading a single private field.
2024-02-22 19:03:55 +00:00
Amelia Cuss c40cfc9fb5 lib.enum: honor enum.nonmember.
Use _EnumDict._member_names to determine which members to consider.
This way we don't need to redo sunder/dunder checks, and `nonmember`s
(introduced in py3.11) are correctly excluded.

This is a defacto public API, given it remains usable from py3.8
until py3.12 inclusive.  (_member_names changes from a list to a
keys-only dict for performance reasons in py3.11, but they iterate the
same.) In current Python main (i.e. what will most likely be 3.13), a
"member_names" property is added which returns those keys.
2024-02-19 23:06:22 +00:00
Wanda 890e099ec3 Implement RFC 45: Move hdl.Memory to lib.Memory. 2024-02-19 22:24:58 +00:00
Wanda 6d65dc1366 hdl, back.rtlil: track and emit module/submodule locations. 2024-02-19 21:41:32 +00:00
Wanda 188eb8d453 back.rtlil: emit wire signedness according to Signal signedness. 2024-02-16 22:03:30 +00:00
Wanda 6058ad35cf hdl._ast: make Shape immutable and hashable.
Fixes #1127.
2024-02-16 15:21:05 +00:00
Wanda 24a392887a Implement RFC 43: Rename reset= to init=. 2024-02-15 22:52:24 +00:00
Catherine 52842ee524 docs: fix link rot. 2024-02-15 19:58:19 +00:00
Wanda e3324e1456 hdl._dsl: fix using 0-width Switch with integer keys.
Fixes #1133.
2024-02-14 19:13:14 +00:00
Wanda 5ffb48b5fb hdl._ast: fix using 0-width Switch with integer keys.
This comes up in `AssignmentLegalizer`-produced `Switch`es for
`ArrayProxy`.
2024-02-14 11:52:35 +00:00
Wanda 0ecd06a7e5 sim: fix using 0-width Switch. 2024-02-14 11:51:19 +00:00
Catherine b9c9948038 docs: use :py: role for inline Python code, not :pc:.
I originally picked :pc: as it is short for "python code", but it is
obscure and :py: is not taken, so a much more obvious role can be used
instead. Also, we all typo :pc: as :py: all the time anyway.
2024-02-13 10:38:36 +00:00
Catherine 3cb5f63aba _toolchain.yosys: add JavaScript (Pyodide) support.
In this environment it's not feasible, or at least it's not documented
how, to distribute JavaScript code by packaging it as a wheel; only
Wasm code (as shared objects) can be distributed this way. The current
`amaranth-yosys` strategy would not work even though wheels can be
installed on Pyodide, and Yosys will need to be explicitly provided by
the environment instead.

The implementation is sufficiently generic that non-Pyodide hosts could
potentially make use of it, though it doesn't seem like any exist at
the moment.
2024-02-13 07:31:53 +00:00
Catherine 9aebf49565 sim.pysim: only import pyvcd when needed.
In some environments (e.g. Pyodide) it may be advantageous to not load
this library, and with the import at file level, it makes the entire
simulator unusable, not just `PySimEngine.write_vcd`.

This might also help people whose Python environments are unusually
broken, whom we've historically accommodated.
2024-02-13 07:31:53 +00:00
Wanda a0c8b18546 vendor._intel: use dff instead of $dff.
Fixes #1046.
2024-02-13 06:14:59 +00:00
Catherine 3867623727 docs/reference: describe out-of-bounds behavior of bit_select/word_select. 2024-02-13 05:44:52 +00:00
Catherine 2dea83cffd docs/reference: minor fixes. 2024-02-13 05:44:52 +00:00
Wanda 1dc1d2d709 vendor.lattice_ice40: use SB_DFF instead of $dff. 2024-02-13 05:42:31 +00:00
Catherine eebb6ec3bb back.verilog: require Yosys 0.38.
This avoids the awkward requirement due to the bug in Yosys 0.37, and
will soon be required anyway once the `$check` cell is emitted.
2024-02-13 05:27:23 +00:00
Wanda 0da439cce1 hdl._ast: deprecate ValueCastable.lowermethod. 2024-02-13 05:06:06 +00:00
Wanda e2fd819742 hdl._ast: fix shift_right and as_signed edge cases. 2024-02-13 04:52:38 +00:00
Catherine 0056e982c5 docs/reference: document Value, ValueCastable, ValueLike.
Co-authored-by: Wanda <wanda@phinode.net>
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
2024-02-13 03:22:04 +00:00
Wanda 4a3a9a90e8 hdl._nir: implement __repr__ on NIR classes. 2024-02-13 01:12:44 +00:00
Wanda 4014f6429c Implement RFC 27 amendment: deprecate add_sync_process, not add_process. 2024-02-12 18:26:48 +00:00
Wanda 18e5bcd6f7 hdl._nir: fix docstring typos. 2024-02-11 16:34:12 +00:00
Catherine 84709e2f00 hdl: remove ValueKey, ValueDict, ValueSet.
These aren't used internally anymore and haven't been used in any code
published on GitHub, so they are simply removed rather than deprecated.
2024-02-11 13:50:06 +00:00
Catherine 6f44438e58 hdl._ir,hdl._nir,back.rtlil: new intermediate representation.
The new intermediate representation will enable global analyses
on Amaranth code without lowering it to another representation
such as RTLIL.

This commit also changes the RTLIL builder to use the new IR.

Co-authored-by: Wanda <wanda@phinode.net>
2024-02-11 09:03:49 +00:00
Catherine 78981232d9 hdl.xfrm: add assignment legalizer.
Co-authored-by: Wanda <wanda@phinode.net>
2024-02-11 09:03:49 +00:00
Catherine 10117607a3 build.plat: fix toolchain environment variable check, #2.
Fixes typo introduced in commit 78b90fba.
2024-02-11 08:21:06 +00:00
Wanda 05ac36751a sim: prefix fields with \.
Fixes #1001.
2024-02-09 21:15:34 +00:00
Wanda 45dbce13df hdl: consistently use "comb" for combinatorial domain.
Fixes #1097.
2024-02-09 19:32:55 +00:00
Wanda b6c5294e50 hdl.MemoryInstance: refactor and add first-class simulation support. 2024-02-09 17:36:15 +00:00
Wanda 6e06fc013f hdl.ir: associate statements with domains.
Fixes #1079.
2024-02-09 05:33:16 +00:00
Wanda 09854fa775 hdl.ast: make it impossible to construct *Castable instances.
Fixes #1072.
2024-02-09 05:26:58 +00:00
Catherine ace7aea375 lib.wiring: track member source locations.
The source location is set to the place where `In`/`Out` was created.

The source location of the instantiation is tracked but overwritten;
we will need to change the internal structure storing those to be able
to include both.

Fixes #1085.
2024-02-08 16:04:44 +00:00
Catherine 78b90fbafa build.plat,vendor: fix toolchain environment variable check.
The bug was introduced in commit 15b6068c. A changelog entry was also
missing.

Fixes #1089.
2024-02-08 11:37:59 +00:00
Daniel Estévez d8f70be4d9 xilinx: use FDPE instances to implement get_async_ff_sync()
This closes #721 by implementing get_async_ff_sync() using FDPE
primitives to obtain exactly the netlist that we want. This consits
of a chain of N FPDEs (by default N = 2) with all their PRE pins
connected to the reset for a positive edge reset or to the ~reset
for a negative edge reset. The D pin of the first FDPE in the chain
is connected to GND.

To make timing analysis work correctly, two new attributes are
introduced: amaranth.vivado.false_path_pre and
amaranth.vivado.max_delay_pre. These work similarly to
amaranth.vivado.false_path and amaranth.vivado.max_delay, but affect
only the PRE pin, which is what is needed for this synchronizer.
The TCL has been modified to generate constraints using these
attributes, and there are comments explaining how to use the attributes
directly in an XDC file in case the user wants to manage their XDC
file manually instead of using the TCL.
2024-02-08 11:30:51 +00:00
Catherine 9e75962c35 Implement RFC 27: Testbench processes for the simulator.
Co-authored-by: Wanda <wanda@phinode.net>
2024-02-06 23:12:07 +00:00
Wanda f48b8650c4 sim: fix simulation loop when process catches an injected exception. 2024-02-06 18:55:11 +00:00
Catherine 15b6068c57 Remove features deprecated in past releases. 2024-02-06 15:55:05 +00:00
Vegard Storheil Eriksen 5e2f3b7992 Implement RFC 42: Const from shape-castable. 2024-02-06 10:18:12 +00:00
Wanda 089213e19f Implement RFC 46: Change Shape.cast(range(1)) to unsigned(0). 2024-02-06 10:05:10 +00:00
Catherine 1fe7bd010f hdl: remove subclassing of AnyValue and Property.
This subclassing is unnecessary and makes downstream code more complex.
In the new IR, they are unified into cells with the same name anyway.
Even before that, this change simplifies things.
2024-02-05 05:58:12 +00:00
Wanda 115954b4d9 lib.fifo: add Memory as submodules instead of its ports. [NFC]
This makes the generated netlist very slightly nicer.
2024-01-31 21:14:08 +00:00
Catherine 357ffb680c hdl: remove Repl per RFC 10.
Closes #770.
2024-01-31 03:01:35 +00:00
Catherine 4da8adf7ba back.rtlil: remove _SyncBuilder. NFC
Amaranth doesn't emit sync rules for a while since these are private
for the Yosys Verilog frontend.
2024-01-31 02:47:52 +00:00
Catherine 572a60d838 hdl: add missing compatibility shims.
These were originally planned to be committed as a part of 5dd1223c,
but were lost during rebasing.
2024-01-31 02:05:17 +00:00
Wanda 1506f08b81 sim: use Value.cast on traces.
See kuznia-rdzeni/coreblocks#357.
2024-01-30 23:20:31 +00:00
Catherine ea3d6c9557 docs/reference: document compat guarantee, importing, shapes.
This commit also contains a related semantic change: it adds `Shape`
and `ShapeCastable` to the `__all__` list in `amaranth.hdl`. This is
consistent with the policy that is laid out in the new documentation,
which permits such additions without notice.

Co-authored-by: mcclure <mcclure@users.noreply.github.com>
2024-01-30 22:54:18 +00:00
Catherine 5dd1223cf8 amaranth.hdl: start all private names with an underscore.
This change completes commit 9dc0617e and makes all the tests pass.
It corresponds with the ongoing langauge reference documentation effort.

Fixes #781.
2024-01-30 17:20:45 +00:00
Catherine cf83193bf9 amaranth.hdl: rename internal modules to begin with an underscore.
This change completely breaks the library. It is done separately just
to make sure git tracks renames as such.
2024-01-30 17:20:45 +00:00
Catherine 8678d5fa14 hdl.dsl: warn if a case is defined after a default case. 2024-01-30 02:54:48 +00:00
Wanda e9299ccd0e hdl.ast: change warning on out-of-range reset to an error, improve it.
Fixes #1019.
2024-01-30 02:35:26 +00:00
Catherine 65d77f03fe back.verilog: forbid Yosys version range with dangling else bug.
Fixes #1049.
2024-01-24 16:45:22 +00:00
Catherine b3639c4cc5 utils: fix docstring syntax. 2024-01-22 23:25:14 +00:00
Adam Greig db7e64960c lib.crc: make module documentation introduction consistent with other stdlib modules. 2024-01-19 08:57:57 +00:00
Wanda b40c18fb00 hdl.ast: suggest bit_select or word_select when indexing with Value.
Fixes #1044.
2024-01-18 20:06:55 +00:00
Wanda 9e9790377a back.rtlil: fix emitting ROMs 2024-01-18 06:40:12 +00:00