I originally picked :pc: as it is short for "python code", but it is
obscure and :py: is not taken, so a much more obvious role can be used
instead. Also, we all typo :pc: as :py: all the time anyway.
In this environment it's not feasible, or at least it's not documented
how, to distribute JavaScript code by packaging it as a wheel; only
Wasm code (as shared objects) can be distributed this way. The current
`amaranth-yosys` strategy would not work even though wheels can be
installed on Pyodide, and Yosys will need to be explicitly provided by
the environment instead.
The implementation is sufficiently generic that non-Pyodide hosts could
potentially make use of it, though it doesn't seem like any exist at
the moment.
In some environments (e.g. Pyodide) it may be advantageous to not load
this library, and with the import at file level, it makes the entire
simulator unusable, not just `PySimEngine.write_vcd`.
This might also help people whose Python environments are unusually
broken, whom we've historically accommodated.
The new intermediate representation will enable global analyses
on Amaranth code without lowering it to another representation
such as RTLIL.
This commit also changes the RTLIL builder to use the new IR.
Co-authored-by: Wanda <wanda@phinode.net>
The source location is set to the place where `In`/`Out` was created.
The source location of the instantiation is tracked but overwritten;
we will need to change the internal structure storing those to be able
to include both.
Fixes#1085.
This closes#721 by implementing get_async_ff_sync() using FDPE
primitives to obtain exactly the netlist that we want. This consits
of a chain of N FPDEs (by default N = 2) with all their PRE pins
connected to the reset for a positive edge reset or to the ~reset
for a negative edge reset. The D pin of the first FDPE in the chain
is connected to GND.
To make timing analysis work correctly, two new attributes are
introduced: amaranth.vivado.false_path_pre and
amaranth.vivado.max_delay_pre. These work similarly to
amaranth.vivado.false_path and amaranth.vivado.max_delay, but affect
only the PRE pin, which is what is needed for this synchronizer.
The TCL has been modified to generate constraints using these
attributes, and there are comments explaining how to use the attributes
directly in an XDC file in case the user wants to manage their XDC
file manually instead of using the TCL.
This subclassing is unnecessary and makes downstream code more complex.
In the new IR, they are unified into cells with the same name anyway.
Even before that, this change simplifies things.
This commit also contains a related semantic change: it adds `Shape`
and `ShapeCastable` to the `__all__` list in `amaranth.hdl`. This is
consistent with the policy that is laid out in the new documentation,
which permits such additions without notice.
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
This change completes commit 9dc0617e and makes all the tests pass.
It corresponds with the ongoing langauge reference documentation effort.
Fixes#781.
Reexports of `amaranth.utils` functions are removed from
`amaranth._utils` to avoid a circular import issue (for `deprecated`).
Since this is a private module, this should not be a problem.
This ensures things like `Const(1.5)` raise an error.
`int(operator.index())` is used since `operator.index(True)` on Python
3.9 and earlier returns `True` instead of `1`.
The build scripts generated by Amaranth are designed to be invoked by
directly running them with any shell (some of them will re-invoke
themselves with `bash` specifically, when it's a toolchain requirement),
and they're not currently marked executable, so there's no shebang.
Add a shebang line to improve compatibility with cases where they are
treated as executables in their own right.
Rather than requiring each additional requested trace to be a signal,
all of the signals in the provided value are added to the GTKW file and
to the VCD file if they are not already there. This improves usability
for `lib.data` as struct fields can now be added to traces.
See #790.
This commit adds an entirely private API for describing formatting of
values that is used in the standard library, in departure from our
standing policy of not using private APIs in the standard library.
This is a temporary measure intended to get the version 0.4 released
faster, as it has been years in the making. It is expected that this
API will be made public in the version 0.5 after going through the usual
RFC process.
This commit only adds VCD lines for fields defined in `lib.data.Layout`
when using `sim.pysim`. The emitted RTLIL and Verilog remain the same.
It is expected that when `sim.cxxsim` lands, RTLIL/Verilog output will
include aliases for layout fields as well.
The value representation API also handles formatting of enumerations,
with no changes visible to the designer. The implementation of
`Signal(decoder=)` is changed as well to use the new API, with full
backwards compatibility and no public API changes.
Co-authored-by: Wanda <wanda@phinode.net>
Although `@property` is the most common case, any descriptors are now
properly supported.
The special casing of methods goes away as they work by having functions
implement the descriptor protocol. (`__get__` has some special behavior
to make this possible.)
This is some of the most cursed code I have ever written, yet it is
obviously necessary.
At the moment there are two issues with assignment of names in pysim:
1. Names are not deduplicated. It is possible (and frequent) for names
to be included twice in VCD output.
2. Names are different compared to what is emitted in RTLIL, Verilog,
or CXXRTL output.
This commit fixes issue (1), and issue (2) will be fixed by the new IR.
On Python <3.10, classes without annotations do not get an
`__annotations__` member at all, so the `getattr` on a subclass falls
back to the parent class `__annotations__`, attempting to create
signature members twice. Fix that by looking at the `__dict__` instead.
While the capability of providing signatures for components that are not
parametric is useful, most Amaranth gateware is heavily parameterized,
and the capability is not worth making most subclasses Liskov-incompatible
with the base class (where the derived class would not provide `signature`
as a class method anymore).
This was introduced in commit 44711b7d, and was never used within
Amaranth itself. While technically a breaking change I think this
will not cause enough breakage to warrant a deprecation cycle
(nor can we make this a deprecation this without a lot of work).
The attribute sees essentially no use and the information is much
better served by putting it in the module name. In addition this
means that the entire tree can be renamed simply by renaming the top
module.
Tools like GTKWave show the names of the instances, not the modules,
so they are not affected by the longer names.
It was thought previously (by me) that adding a wire that does
nothing to an empty subfragment is enough to prevent it from being
treated as a blackbox. This is enough for Yosys but not Vivado.
Another workaround could probably be used that satisfies both, but
instead let's just not translate any empty subfragments.
This doesn't account for the case of the empty toplevel, but that
does not seem worth addressing.
Fixes#899.
Tracking #879.
The directions of signals in `Pin` make it convenient to use a pin
signature in a component, such as in:
class LEDDriver(Component):
pins: Out(Signature({"o": Out(1)}))
led_driver = LEDDriver()
connect(led_driver.pins, platform.request("led"))
The `platform.request` call, correspondingly, returns a flipped `Pin`
object.
The design decision of using split memory ports in the internal
representation (copied from Yosys) was misguided and caused no end
of misery. Remove any uses of `$memrd`/`$memwr` and lower memories
directly to a combined memory cell, currently the RTLIL one.
