whitequark
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a6a8703a0e
|
back.pysim: simplify.
|
2018-12-14 20:45:45 +00:00 |
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|
whitequark
|
7e3cf26cf8
|
back.pysim: revert 70ebc6f2.
|
2018-12-14 19:46:08 +00:00 |
|
|
whitequark
|
71304c9fe7
|
back.pysim: fix implicit boolean conversion.
|
2018-12-14 19:08:06 +00:00 |
|
|
whitequark
|
fe5fb34fae
|
back.pysim: squash one level of hierarchy.
There's really no point in the "top" node.
|
2018-12-14 18:53:21 +00:00 |
|
|
whitequark
|
70ebc6f2c1
|
back.pysim: implement blocking assignment semantics correctly.
|
2018-12-14 18:47:12 +00:00 |
|
|
whitequark
|
120d817123
|
back.pysim: undriven sync signals should return to previous value.
|
2018-12-14 17:25:48 +00:00 |
|
|
whitequark
|
4f5b4a9bf4
|
back.pysim: in simulator sync processes, start by waiting for a tick.
This matches Migen behavior and also makes more sense.
|
2018-12-14 17:05:11 +00:00 |
|
|
whitequark
|
e230383aac
|
back.pysim: make initial phase configurable.
|
2018-12-14 16:46:16 +00:00 |
|
|
whitequark
|
0ef5ced492
|
compat.sim: match clock period.
|
2018-12-14 16:39:52 +00:00 |
|
|
whitequark
|
17d26c8329
|
compat: add run_simulation shim.
|
2018-12-14 16:22:18 +00:00 |
|
|
whitequark
|
88970ee29f
|
pysim.back: fix add_sync_process wrapper to handle signals correctly.
|
2018-12-14 16:21:53 +00:00 |
|
|
whitequark
|
3bc3647380
|
compat.fhdl.module: fix specials.
|
2018-12-14 16:14:08 +00:00 |
|
|
whitequark
|
3b23645fb7
|
compat: add fhdl.specials.TSTriple shim.
|
2018-12-14 16:09:51 +00:00 |
|
|
whitequark
|
7200346249
|
genlib.io: import TSTriple from Migen.
|
2018-12-14 16:09:51 +00:00 |
|
|
whitequark
|
50ba443f92
|
fhdl.ast: fix Switch with constant test.
|
2018-12-14 16:09:51 +00:00 |
|
|
whitequark
|
a0d555a9fc
|
compat: add genlib.cdc.MultiReg shim.
|
2018-12-14 16:01:38 +00:00 |
|
|
whitequark
|
baba47251c
|
compat.fhdl.module: update deprecation messages.
|
2018-12-14 16:01:38 +00:00 |
|
|
whitequark
|
9307a31678
|
back.pysim: Simulator({gtkw_signals→traces}=).
|
2018-12-14 15:23:22 +00:00 |
|
|
whitequark
|
e3f32a1faf
|
back.pysim: better naming. NFC.
|
2018-12-14 15:21:13 +00:00 |
|
|
whitequark
|
474d46ced8
|
back.pysim: implement most operators and add tests.
|
2018-12-14 14:21:22 +00:00 |
|
|
whitequark
|
d9aaf0114b
|
back.pysim: close .vcd/.gtkw files on context manager exit.
|
2018-12-14 13:59:03 +00:00 |
|
|
whitequark
|
1655b59d1b
|
back.pysim: show more legible names for processes in errors.
|
2018-12-14 13:50:19 +00:00 |
|
|
whitequark
|
625c55a3b8
|
back.pysim: throw exceptions back at processes.
|
2018-12-14 13:43:25 +00:00 |
|
|
whitequark
|
654722ce14
|
back.pysim: add gtkw traces even more robustly.
|
2018-12-14 13:43:08 +00:00 |
|
|
whitequark
|
7d3f7f277a
|
back.pysim: accept (and evaluate) generator functions.
|
2018-12-14 13:32:30 +00:00 |
|
|
whitequark
|
7fc9f98b98
|
back.pysim: skip VCD signal population if VCD is not requested.
|
2018-12-14 13:32:30 +00:00 |
|
|
whitequark
|
3ad79ec690
|
back.pysim: allow processes to evaluate expressions.
|
2018-12-14 13:32:30 +00:00 |
|
|
whitequark
|
151d079f01
|
fhdl.ir: oops, we defined DomainError twice.
|
2018-12-14 12:59:54 +00:00 |
|
|
whitequark
|
dd00b5e2d6
|
back.pysim: more general clean-up.
|
2018-12-14 12:46:04 +00:00 |
|
|
whitequark
|
1b7f8c7950
|
back.pysim: general clean-up.
|
2018-12-14 12:22:03 +00:00 |
|
|
whitequark
|
105113f1d8
|
back.pysim: accept any valid assignments from processes.
|
2018-12-14 12:18:41 +00:00 |
|
|
whitequark
|
240a40c2c2
|
back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.
|
2018-12-14 10:57:13 +00:00 |
|
|
whitequark
|
7d91dd56c8
|
fhdl.xfrm: implement DomainLowerer.
|
2018-12-14 10:56:53 +00:00 |
|
|
whitequark
|
b34c1a9ad0
|
back.pysim: undriven comb signals should return to reset value.
|
2018-12-14 09:12:38 +00:00 |
|
|
whitequark
|
b58715c5dc
|
ast, back.pysim: allow specifying user-defined decoders for signals.
|
2018-12-14 09:02:29 +00:00 |
|
|
whitequark
|
bb843cb40c
|
back.pysim: fix completely broken codegen for Switch.
|
2018-12-14 08:51:36 +00:00 |
|
|
whitequark
|
6aefd0c04c
|
back.pysim: raise an exception if delta cycles blow a process deadline.
|
2018-12-14 08:10:21 +00:00 |
|
|
whitequark
|
a10791e160
|
back.pysim: if requested, write a gtkw file with a useful preset.
|
2018-12-14 08:04:29 +00:00 |
|
|
whitequark
|
cb998d891b
|
back.pysim: explain how delta cycles work.
|
2018-12-14 07:26:26 +00:00 |
|
|
whitequark
|
e4d08d2855
|
back.pysim: delay clock processes by one half period.
Makes it easier to see initial delta cycles.
|
2018-12-14 05:17:43 +00:00 |
|
|
whitequark
|
3bb7a87e0f
|
back.pysim: implement "sync processes", like migen.sim generators.
|
2018-12-14 05:13:58 +00:00 |
|
|
whitequark
|
d791b77cc8
|
back.pysim: allow suspending processes until a tick in a domain.
|
2018-12-14 04:33:06 +00:00 |
|
|
whitequark
|
3e59d857e1
|
back.pysim: use bare ints for signal values (-5% runtime).
|
2018-12-14 03:05:57 +00:00 |
|
|
whitequark
|
b09f4b10ee
|
back.pysim: collect handlers before running (-5% runtime).
|
2018-12-13 18:34:44 +00:00 |
|
|
whitequark
|
a7ebc02bdd
|
back.pysim: allow multiple registered handlers per signal.
|
2018-12-13 18:28:11 +00:00 |
|
|
whitequark
|
6a4004ef8d
|
back.pysim: fix handling of process termination.
|
2018-12-13 18:17:58 +00:00 |
|
|
whitequark
|
fb27c2520b
|
back.pysim: new simulator backend (WIP).
|
2018-12-13 18:02:46 +00:00 |
|
|
whitequark
|
71f1f717c4
|
fhdl.cd: rename ClockDomain signals together with domain.
|
2018-12-13 15:24:55 +00:00 |
|
|
whitequark
|
07c818e077
|
fhdl.ir: move Fragment prepare logic from back.rtlil.
|
2018-12-13 14:34:07 +00:00 |
|
|
whitequark
|
ac498414ab
|
back.verilog: remove debug code.
|
2018-12-13 13:42:54 +00:00 |
|
|
whitequark
|
90f1503c91
|
fhdl.ir: record port direction explicitly.
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
|
2018-12-13 13:12:31 +00:00 |
|
|
whitequark
|
6251c95d4e
|
compat.genlib.fsm: import/wrap Migen code.
|
2018-12-13 12:41:19 +00:00 |
|
|
whitequark
|
9661e897e6
|
fhdl.ir: a subfragment's input that we don't drive is also our input.
|
2018-12-13 11:50:56 +00:00 |
|
|
whitequark
|
bb04c9e0da
|
fhdl, back: trace and emit source locations of values.
|
2018-12-13 11:44:06 +00:00 |
|
|
whitequark
|
859c2dbcf0
|
back.rtlil: never give subfragment cells names starting with $.
|
2018-12-13 11:30:16 +00:00 |
|
|
whitequark
|
b150f1915d
|
fhdl.ir: don't crash propagataing ports in empty fragments.
|
2018-12-13 11:25:49 +00:00 |
|
|
whitequark
|
72257b6935
|
fhdl.ir: implement clock domain propagation.
|
2018-12-13 11:01:03 +00:00 |
|
|
whitequark
|
fde2471963
|
fhdl.ir: remove iter_domains().
|
2018-12-13 10:18:57 +00:00 |
|
|
whitequark
|
f4340c19bb
|
fhdl: cd_name→domain.
|
2018-12-13 10:15:01 +00:00 |
|
|
whitequark
|
c5087edfa5
|
fhdl.cd: add tests.
|
2018-12-13 09:19:16 +00:00 |
|
|
whitequark
|
9bee90f1bd
|
fhdl.xfrm: implement DomainRenamer.
|
2018-12-13 08:57:14 +00:00 |
|
|
whitequark
|
8963ab5d9f
|
fhdl.xfrm: add test for ControlInserter with subfragments.
|
2018-12-13 08:45:10 +00:00 |
|
|
whitequark
|
19aa404628
|
fhdl.xfrm: add tests for ResetInserter, CEInserter.
|
2018-12-13 08:39:02 +00:00 |
|
|
whitequark
|
b1a89ef5fd
|
fhdl.ir: add tests for port propagation.
|
2018-12-13 08:09:39 +00:00 |
|
|
whitequark
|
a797e27573
|
fhdl.dsl: add tests for lowering. 99% branch coverage.
|
2018-12-13 07:33:59 +00:00 |
|
|
whitequark
|
d2e2d00e45
|
fhdl.cd: rename ClockDomain.{reset→rst}.
|
2018-12-13 07:27:27 +00:00 |
|
|
whitequark
|
e0a81edf4d
|
fhdl.dsl: add tests for submodules.
|
2018-12-13 07:24:28 +00:00 |
|
|
whitequark
|
932f1912a2
|
fhdl.dsl: use less error-prone Switch/Case two-level syntax.
|
2018-12-13 07:11:06 +00:00 |
|
|
whitequark
|
f70ae3bac5
|
fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
|
2018-12-13 06:06:51 +00:00 |
|
|
whitequark
|
5b8708017e
|
fhdl.ast: fix Switch._?hs_signals() for switch without statements.
|
2018-12-13 05:00:44 +00:00 |
|
|
whitequark
|
4e32f6b8de
|
back.verilog: detect undriven public wires using Yosys.
This should never happen, and is certainly a logic bug in nMigen.
|
2018-12-13 04:59:48 +00:00 |
|
|
whitequark
|
27d3dfc453
|
back.rtlil: fix swapped operands in sync assign.
|
2018-12-13 04:34:22 +00:00 |
|
|
whitequark
|
6c7f98e964
|
back.rtlil: explain logic for CD reset insertion.
|
2018-12-13 03:51:00 +00:00 |
|
|
whitequark
|
2c67a620ee
|
back.rtlil: explicitly set the top module.
|
2018-12-13 03:50:04 +00:00 |
|
|
whitequark
|
4df5c5de65
|
fhdl.ir: explain how port enumeration works.
|
2018-12-13 03:31:13 +00:00 |
|
|
whitequark
|
f86ec1e7ef
|
back.rtlil: explain how RTLIL conversion works.
|
2018-12-13 03:22:01 +00:00 |
|
|
whitequark
|
bfd0011aee
|
fhdl.ir: make sure clocks and resets of used CDs appear as inputs.
|
2018-12-13 02:43:22 +00:00 |
|
|
whitequark
|
a17a9e355d
|
back.rtlil: give clocks and resets nicer names.
|
2018-12-13 02:43:02 +00:00 |
|
|
whitequark
|
22c76e5f90
|
compat.fhdl.module: implement finalization.
|
2018-12-13 02:36:15 +00:00 |
|
|
whitequark
|
b42620e490
|
back.rtlil: match shape of $mux ports A/B/Y.
|
2018-12-13 02:35:46 +00:00 |
|
|
whitequark
|
17767642be
|
tracer: add support for Python 3.7.
|
2018-12-13 02:20:00 +00:00 |
|
|
whitequark
|
f0f4c0ce61
|
fhdl.ast: bits_sign→shape.
|
2018-12-13 02:06:58 +00:00 |
|
|
whitequark
|
dc486ad8b9
|
fhdl.ast: add tests for most logic.
|
2018-12-13 02:06:55 +00:00 |
|
|
whitequark
|
b4dab74b2e
|
compat.fhdl.{module,structure}: import/wrap Migen code (WIP).
|
2018-12-12 15:47:34 +00:00 |
|
|
whitequark
|
356852a570
|
compat.fhdl.bitcontainer: import/wrap Migen code.
|
2018-12-12 15:22:34 +00:00 |
|
|
whitequark
|
1d4d00aac6
|
fhdl.ast.Signal: implement .like().
|
2018-12-12 14:43:19 +00:00 |
|
|
whitequark
|
ad9b45adcd
|
fhdl.ir: fix port threading code.
|
2018-12-12 13:00:50 +00:00 |
|
|
whitequark
|
0fac1f8d0f
|
fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
|
2018-12-12 12:38:24 +00:00 |
|
|
whitequark
|
00f0b950f6
|
fhdl.ast.Signal: fix typo.
|
2018-12-12 12:37:30 +00:00 |
|
|
whitequark
|
aab01d9e59
|
fhdl.ast.Signal: implement attrs field.
|
2018-12-12 11:30:40 +00:00 |
|
|
whitequark
|
c05c189ece
|
genlib.cdc.MultiReg: self.regs should be a private field.
|
2018-12-12 10:52:32 +00:00 |
|
|
whitequark
|
4eadc1629a
|
fhdl.ast.Signal: implement width derivation from min/max.
|
2018-12-12 10:43:09 +00:00 |
|
|
whitequark
|
bc60631d68
|
genlib.cdc.MultiReg: pull in from Migen.
|
2018-12-12 10:12:35 +00:00 |
|
|
whitequark
|
263d577323
|
fhdl.ast.Signal: implement reset_less signals.
|
2018-12-12 10:11:16 +00:00 |
|
|
whitequark
|
1d46ffb591
|
fhdl.ast.Signal: assign an internal name if tracer fails.
|
2018-12-12 10:08:56 +00:00 |
|
|
whitequark
|
6d5878a0ee
|
fhdl.dsl: allow f.sync["dom"] as a synonym of f.sync.dom.
|
2018-12-12 10:00:00 +00:00 |
|
|
whitequark
|
851ed06769
|
ClockDomain.{rst→reset}, for consistency with ResetInserter.
nmigen.compat.ClockDomain would alias this, for Migen compatibility.
|
2018-12-12 09:49:02 +00:00 |
|
|
whitequark
|
4d3258013d
|
Initial commit.
|
2018-12-12 03:18:44 +00:00 |
|