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Author SHA1 Message Date
Catherine 7044e09110 hdl.ast: remove Shape<>tuple comparisons. 
See #691.

I missed this in commit 29502442.
 2023-01-31 15:23:06 +00:00
Catherine 29502442fb hdl.ast: remove Shape<>tuple casts. 
Closes #691.
 2023-01-31 12:58:29 +00:00
Arusekk de6b69370f hdl.ast: Do not warn on int Enums in Cat. 
This aligns with the behavior for plain Enums.
 2023-01-22 23:40:39 +00:00
Arusekk 58a0c68279 hdl.ast: allow typed int enums in Value.cast. 2023-01-22 23:40:39 +00:00
Catherine da26f1c915 hdl,back,sim: accept .as_signed() and .as_unsigned() on LHS. 
These operators are ignored when they are encountered on LHS, as
the signedness of the assignment target does not matter in Amaranth.
.as_signed() appears on LHS of assigns to signed aggregate fields.
 2022-09-24 07:19:47 +00:00
Catherine bf16acf2f0 hdl.ast: implement ShapeCastable (like ValueCastable). 
Refs #693.
 2022-09-24 07:19:03 +00:00
Catherine 0723f6bac9 hdl.ast: recursively cast ValueCastable objects to values. 2022-09-24 07:18:57 +00:00
Bastian Löher 02364a4fd7 sim: Fix clock phase in add_clock having to be specified in ps. 2022-02-04 16:46:52 +00:00
Irides 538c14116c sim.pysim: use "bench" as a top level root for testbench signals. 
Fixes #561.
 2021-12-16 15:46:05 +00:00
Catherine 847e46927b back.{verilog,rtlil}: fix commit d83c4a1b. 
The `ports` argument has been passed implicitly, via `**kwargs`, and
that was broken during the deprecation.

Closes #659.
 2021-12-14 10:47:04 +00:00
Irides d83c4a1b21 back.{rtlil,verilog}: deprecate implicit ports. 
Fixes #630.
 2021-12-13 12:21:44 +00:00
modwizcode 1ee2482c6b sim: represent time internally as 1ps units 
Using floats to represent simulation time internally isn't ideal
instead use 1ps internal units while continuing to use a floating
point based interface for compatibility.

Fixes #535.
 2021-12-13 08:15:11 +00:00
whitequark 7c161957bf build.dsl: check type of resource number. 
Fixes #599.
 2021-12-11 13:37:15 +00:00
whitequark 7e2b72826f sim.core: warn when driving a clock domain not in the simulation. 
Closes #566.
 2021-12-11 13:22:24 +00:00
whitequark ac13a5b3c9 sim._pyrtl: reject very large values. 
A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.
 2021-12-11 13:00:46 +00:00
whitequark 599615ee3a hdl.ir: reject elaboratables that elaborate to themselves. 
Fixes #592.
 2021-12-11 12:40:05 +00:00
whitequark 66295fa388 sim.pysim: refuse to write VCD files with whitespace in signal names. 
Closes #595.
 2021-12-11 11:12:25 +00:00
whitequark b452e0e871 hdl.ast: support division and modulo with negative divisor. 
Fixes #621.

This commit bumps the Yosys version requirement to >=0.10.
 2021-12-11 10:25:48 +00:00
whitequark 44b8bd29af hdl.ast: warn on bare integer value used in Cat()/Repl(). 
Fixes #639.
 2021-12-11 08:18:33 +00:00
whitequark de7c9acb19 _utils: don't crash trying to flatten() strings. 
Fixes #614.
 2021-12-11 07:39:35 +00:00
whitequark 909a3b8be7 Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
whitequark 11914a1e67 hdl.ast: improve interaction of ValueCastable with custom __getattr__. 
Avoid calling `__getattr__("_ValueCastable__lowered_to")` when
a ValueCastable has custom `__getattr__` implementation; this avoids
the need for downstream code to be aware of this implementataion
detail.
 2021-10-03 20:28:07 +00:00
whitequark e88d283ed3 hdl.ast: simplify Mux implementation. 2021-10-02 14:18:02 +00:00
whitequark 65499d5c45 hdl.ast: add tests for casting bare integers in {Cat,Repl}. 2021-10-02 13:18:11 +00:00
Robin Ole Heinemann b38b2cdad7 test.test_hdl_ast.OperatorTestCase: remove duplicate test_bool 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann 2d85f888d6 tests: rename tests with duplicate names 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann b93a54ac58 tests.test_hdl_cd.ClockDomainTestCase.test_name: actually test domain with cd_ prefix 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann 25caf4045b *: remove unused imports 2021-05-18 20:18:55 +00:00
Thomas Watson d09dedfb48 tests.hdl.dsl: add tests for mis-nested Switch/Case and FSM/State statements 2021-05-11 02:41:32 +00:00
Thomas Watson 7443f89200 hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements 2021-05-11 02:41:32 +00:00
whitequark c30dcea24d hdl.ast: handle int subclasses as slice start/stop values. 
Fixes #601.
 2021-03-18 23:52:23 +00:00
Robin Ole Heinemann 9af8201727 lib.fifo.AsyncFIFOBuffered: fix output register accounting 2021-01-06 01:05:46 +00:00
Robin Ole Heinemann 2a7a3aef87 lib.fifo.AsyncFIFOBuffered: fix FFSynchronizer latency 2021-01-06 01:05:46 +00:00
Robin Ole Heinemann d15705cf4f lib.fifo: use proper clock domains in AsyncFIFO tests 2021-01-06 01:05:46 +00:00
whitequark 818c8bc464 hdl.ast: normalize case values to two's complement, not signed binary. 
This was an especially insidious bug because the minus character is
valid in case values but has a completely different meaning (wildcard
rather than sign).

Fixes #559.
 2020-12-12 12:42:12 +00:00
awygle c1ed90807b
nmigen.hdl.rec: restore Record.shape(). 
This method was lost in commit abbebf8e.
 2020-11-17 19:36:58 +00:00
Marcelina Kościelnicka 44318149e0
sim._pyrtl: mask Mux selection operand. 
Otherwise it behaves funny when it's eg. the result of operator ~.
 2020-11-14 15:22:34 +00:00
whitequark d6da4c257b build.plat: TemplatedPlatform.iter_extra_files→Platform.iter_files. 
This function was added in commit 20553b14 in the wrong place, with
the wrong name, and without tests. Fix all that.
 2020-11-10 05:30:30 +00:00
awygle ea94c9cc45
hdl.rec: proxy operators correctly. 
Commit abbebf8e used __getattr__ to proxy Value methods called on 
Record. However, that did not proxy operators like __add__ because
Python looks up the special operator methods directly on the class
and does not run __getattr__ if they are missing.

Instead of using __getattr__, explicitly enumerate and wrap every
Value method that should be proxied. This also ensures backwards
compatibility if more methods are added to Value later.

Fixes #533.
 2020-11-09 20:20:25 +00:00
whitequark bde37fe2f2 hdl.ast: deprecate UserValue in favor of ValueCastable. 
Closes #527.
 2020-11-06 02:21:53 +00:00
whitequark 10fd5cff4b CI: run testsuite with -Werror. 2020-11-06 01:38:03 +00:00
awygle abbebf8efe
hdl.rec: migrate Record from UserValue to ValueCastable. 
Closes #528.
 2020-11-06 01:10:39 +00:00
awygle 06c734992f
hdl.ast: implement ValueCastable. 
Closes RFC issue #355.
 2020-11-06 00:20:54 +00:00
Jaro Habiger b15f0562a6 lib.fifo: fix {r,w}_level in AsyncFIFOBuffered 2020-11-03 09:34:12 +00:00
Jaro Habiger c7014f84ea lib.fifo: fix level on fifo full 2020-11-03 09:20:30 +00:00
Robin Ole Heinemann 05decc43b2 lib.fifo.AsyncFFSynchronizer: check input and output signal width 2020-10-28 00:08:38 +00:00
whitequark e3207b74f4 build.dsl: clean up inversion logic. 
* Add invert= argument to DiffPairs() constructor, like in Pins().
  * Make PinsN() and DiffPairsN() pass invert= to the corresponding
    construtor instead of mutating.
 2020-10-26 19:50:21 +00:00
anuejn d8273a15c3
lib.fifo.AsyncFIFO: fix incorrect latency of r_level. 
Co-authored-by: Andrew Wygle <awygle@gmail.com>
 2020-10-24 14:58:23 +00:00
anuejn ca6fa036f6
tests: make spec directory name unique per test method. 2020-10-22 21:38:44 +00:00
whitequark df70aae887 sim._pyrtl: sign extend RHS of assignment. 
Fixes #502.
 2020-10-22 16:08:38 +00:00