This merges existing code, and also adds support for:
- Virtex, Virtex E (also known as Spartan 2, Spartan 2E)
- Virtex 2, Virtex 2 Pro
- Spartan 3, Spartan 3E (in addition to existing Spartan 3A, Spartan 3A
DSP support)
- Virtex 4
- Virtex 5
- Virtex 6
- ISE synthesis for Series 7
Fixes#552.
When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.
Fixes#456.
Supersedes #457.
Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
Since commit b9799b4c, the discovery mechanism for the Yosys required
to produce Verilog is different from the usual require_tool(); namely
it is possible to produce Verilog without a `yosys` binary on PATH.
Fixes#419.
In some cases, it is necessary to synchronize a reset-like signal but
a new clock domain is not desirable. To address these cases, extract
the implementation of ResetSynchronizer into AsyncFFSynchronizer,
and replace ResetSynchronizer with a thin wrapper around it.
For most toolchains, these are functionally identical, although ports
tend to work a bit better, being the common case. For Vivado, though,
it is necessary to place them on the port because its timing analyzer
considers input buffer delay.
Fixes#301.
Now environment variable overrides no longer infect the build scripts.
_toolchain.overrides is dropped as probably misguided in the first place.
Fixes#251.
This change achieves two related goals.
First, default_rst is no longer assumed to be synchronous to
default_clk, which is the safer option, since it can be connected to
e.g. buttons on some evaluation boards.
Second, since the power-on / configuration reset is inherently
asynchronous to any user clock, the default create_missing_domain()
behavior is to use a reset synchronizer with `0` as input. Since,
like all reset synchronizers, it uses Signal(reset=1) for its
synchronization stages, after power-on reset it keeps its subordinate
clock domain in reset, and releases it after fabric flops start
toggling.
The latter change is helpful to architectures that lack an end-of-
configuration signal, i.e. most of them. ECP5 was already using
a similar scheme (and is not changed here). Xilinx devices with EOS
use EOS to drive a BUFGMUX, which is more efficient than using
a global reset when the design does not need one; Xilinx devices
without EOS use the new scheme. iCE40 requires a post-configuration
timer because of BRAM silicon bug, and was changed to add a reset
synchronizer if user clock is provided.
Although useful for debugging, most external tools often complain
about such attributes (with notable exception of Vivado). As such,
it is better to emit Verilog with these attributes into a separate
file such as `design.debug.v` and only emit the attributes that were
explicitly placed by the user to `design.v`.
This still leaves the (*init*) attribute. See #220 for details.
It's not practical to detect tools within the toolchain environment
for various reasons, so just assume the tools are there if the user
says they are.
Before this commit, the tools would be searched outside the toolchain
environment, which of course would always fail for Vivado, ISE, etc.
On Xilinx devices, flip-flops are reset to their initial state with
an internal global reset network, but this network is deasserted
asynchronously to user clocks. Use BUFGCE and STARTUP to hold default
clock low until after GWE is deasserted.
Previously changed in 27063a3b.
I haven't realized the .bin file is the same as the .bit file without
a small header. That means generating it is free and it's just easier
to let programming tools to be able to always rely on its existence.
