usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity
1429 commits 1 branch 0 tags 3.8 MiB
Commit graph

1429 commits

This branch
This branch
All branches
Author SHA1 Message Date
whitequark f0af0a8449 Run tests on Python 3.10. 2021-11-05 18:40:45 +00:00
whitequark 7c740a85ea Simplify CI workflow. 2021-11-05 18:37:51 +00:00
whitequark a2ef4cb6b8 Add PEP 518 pyproject.toml. 2021-11-05 14:44:31 +00:00
Olivier Galibert 177f1b2e40
vendor.intel: add Mistral toolchain support. 2021-10-14 16:02:22 +00:00
whitequark 11914a1e67 hdl.ast: improve interaction of ValueCastable with custom __getattr__. 
Avoid calling `__getattr__("_ValueCastable__lowered_to")` when
a ValueCastable has custom `__getattr__` implementation; this avoids
the need for downstream code to be aware of this implementataion
detail.
 2021-10-03 20:28:07 +00:00
whitequark fac1b4b2d1 hdl.dsl: simplify. NFC. 2021-10-02 17:00:01 +00:00
whitequark e88d283ed3 hdl.ast: simplify Mux implementation. 2021-10-02 14:18:02 +00:00
whitequark 65499d5c45 hdl.ast: add tests for casting bare integers in {Cat,Repl}. 2021-10-02 13:18:11 +00:00
Anton Blanchard 9f78ac0691
hdl.ast: remove quadratic time complexity in Statement.cast(). 
Using `sum(lst, [])` to flatten a list of lists has quadratic time
complexity. Use `chain.from_iterable()` instead. While not strictly
necessary to improve performance, convert to `map()`.

A test case writing out verilog for a 512k entry FIFO is 120x faster
with this applied.
 2021-09-27 01:00:56 +00:00
H-S-S-11 9834b7e95f
vendor.xilinx: avoid using / for hierarchy in ISE constraint files. 2021-09-25 10:41:23 +00:00
Marcelina Kościelnicka bdbe8bff27 Unify Xilinx platforms into a single class, support more devices 
This merges existing code, and also adds support for:

- Virtex, Virtex E (also known as Spartan 2, Spartan 2E)
- Virtex 2, Virtex 2 Pro
- Spartan 3, Spartan 3E (in addition to existing Spartan 3A, Spartan 3A
  DSP support)
- Virtex 4
- Virtex 5
- Virtex 6
- ISE synthesis for Series 7

Fixes #552.
 2021-09-25 05:04:06 +00:00
Adam Jeliński da8a492be7 _toolchain: Properly set compiler/linker executables on Gentoo 
The `test_toolchain_cxx.py` tests on Gentoo definitely use compiler and
linker set with `_so_cxx`-suffixed executables. Tests use a proper
executable instead of `c++` after this change.

Signed-off-by: Adam Jeliński <ajelinski@antmicro.com>
 2021-09-25 03:35:10 +00:00
Robin Ole Heinemann 23a44f3cb6 vendor.xilinx_{7series,ultrascale}: hierachical -> hierarchical 
Signed-off-by: Robin Ole Heinemann <robin.ole.heinemann@gmail.com>
 2021-08-16 22:17:27 +00:00
Jean-François Nguyen abb2642256 _toolchain: substitute '+' with 'X' in tool_env_var(). 2021-07-17 06:27:44 +00:00
whitequark e974a31022
README: update IRC channel. 2021-05-20 03:07:51 +00:00
Robin Ole Heinemann 78be9e7b67 rpc: fix parsing of negative signed parameters 2021-05-18 20:54:40 +00:00
Robin Ole Heinemann b38b2cdad7 test.test_hdl_ast.OperatorTestCase: remove duplicate test_bool 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann 2d85f888d6 tests: rename tests with duplicate names 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann b93a54ac58 tests.test_hdl_cd.ClockDomainTestCase.test_name: actually test domain with cd_ prefix 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann f570e1bbeb *: remove unused variables 2021-05-18 20:18:55 +00:00
Robin Ole Heinemann 25caf4045b *: remove unused imports 2021-05-18 20:18:55 +00:00
Thomas Watson d09dedfb48 tests.hdl.dsl: add tests for mis-nested Switch/Case and FSM/State statements 2021-05-11 02:41:32 +00:00
Thomas Watson 7443f89200 hdl.dsl: raise SyntaxError for mis-nested If/Elif/Else statements 2021-05-11 02:41:32 +00:00
Adam Greig d824795c2c
vendor.lattice_{ecp5,machxo_2_3l}: remove -forceAll from Diamond scripts. 
Fixes #604.
 2021-04-12 09:48:20 +00:00
whitequark c84d4aff6e CI: fix sri-csl/formal-methods PPA series. 
GHA's Ubuntu has been upgraded to Focal.
 2021-03-19 00:02:02 +00:00
whitequark c30dcea24d hdl.ast: handle int subclasses as slice start/stop values. 
Fixes #601.
 2021-03-18 23:52:23 +00:00
dx-mon f7c2b9419f compat.genlib.roundrobin: fix missing imports 2021-02-04 11:02:27 +00:00
nickoe 746886ca8a
vendor.xilinx_7series: fix tool names for symbiflow. 
Prefix "tools" with symbiflow_ as is done for the QuickLogic Symbiflow
toolchain. Installing symbiflow gives me the tools with the preifx, so I
guess this is the correct way to move forward.
 2021-01-31 18:08:44 +00:00
Katherine Temkin 09de190bd1 vendor.lattice_ecp5: correctly generate OE signaling when xdr=0 
This fixes a logic bug introduced in
6ce2b21e19.
 2021-01-26 09:44:22 +00:00
Adam Greig 6ce2b21e19
vendor.lattice_ecp5: replicate OE signal for each output bit. 
nextpnr can only pack OE FFs into IOLOGIC when there's one OFS1P3DX per
output, rather than one shared instance.
 2021-01-23 18:06:52 +00:00
whitequark a2da34a5bc README: add ChipEleven as a sponsor. 2021-01-23 03:27:31 +00:00
Joel Stanley 490fca5745 docs: Update up_counter to avoid deprecation warning 
nmigen/docs/_code/up_counter.py:44: DeprecationWarning: instead of nmigen.back.pysim.*, use nmigen.sim.*
  from nmigen.back.pysim import Simulator
 2021-01-17 12:56:30 +00:00
Adam Greig 3a4b61c16e
vendor.lattice_ecp5: remove outdated comment in ECP5 platform. 
Starting with nextpnr c6401413a, nextpnr does pack *FS1P3DX
into IOLOGIC cells.
 2021-01-14 11:34:03 +00:00
Robin Ole Heinemann 9af8201727 lib.fifo.AsyncFIFOBuffered: fix output register accounting 2021-01-06 01:05:46 +00:00
Robin Ole Heinemann 2a7a3aef87 lib.fifo.AsyncFIFOBuffered: fix FFSynchronizer latency 2021-01-06 01:05:46 +00:00
Robin Ole Heinemann d15705cf4f lib.fifo: use proper clock domains in AsyncFIFO tests 2021-01-06 01:05:46 +00:00
Robin Ole Heinemann 76efe862fa lib.fifo.AsyncFIFOBuffered: use FFSynchronizer instead of AsyncFFsynchronizer 
AsyncFFsynchronizer only synchronizes one edge
 2021-01-06 01:05:46 +00:00
whitequark b466b724fe Revert "vendor.xilinx_7series: byte swap generated bitstream" 
This reverts commit 14a5c42a8b.
 2020-12-12 22:08:57 +00:00
whitequark 7dde2aac7c hdl.ast: formatting. NFC. 2020-12-12 15:42:23 +00:00
whitequark 818c8bc464 hdl.ast: normalize case values to two's complement, not signed binary. 
This was an especially insidious bug because the minus character is
valid in case values but has a completely different meaning (wildcard
rather than sign).

Fixes #559.
 2020-12-12 12:42:12 +00:00
whitequark 4e7e0b33d5 back.rtlil: give private items an appropriate name. NFCI. 2020-12-12 12:20:49 +00:00
whitequark 59ef6e6a1c build.plat: make verbose work like all other overrides. 
Fixes #497.
 2020-11-24 23:07:09 +00:00
whitequark 90e3504097 vendor.intel: implement add_settings (QSF) and add_constraints (SDC) overrides. 2020-11-24 20:35:58 +00:00
whitequark f1473e483a vendor.xilinx_spartan_3_6: fix typo. 
This was introduced in commit 2f8669ca.

Fixes #549.
 2020-11-22 00:16:02 +00:00
whitequark 39ff7203ba hdl.ast: remove dead code. NFC. 
See #548.
 2020-11-21 17:30:28 +00:00
awygle c1ed90807b
nmigen.hdl.rec: restore Record.shape(). 
This method was lost in commit abbebf8e.
 2020-11-17 19:36:58 +00:00
Marcelina Kościelnicka 44318149e0
sim._pyrtl: mask Mux selection operand. 
Otherwise it behaves funny when it's eg. the result of operator ~.
 2020-11-14 15:22:34 +00:00
Jan Kowalewski adef3b2e7b vendor.quicklogic: enable SoC clock configuration 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2020-11-13 16:27:15 +00:00
whitequark 36bc1d2b4d vendor.quicklogic: write OpenOCD scripts as part of build process. 
The OpenOCD scripts for EOS-S3 are roughly equivalent to SVF files
for a more traditional FPGA, which we also produce, for some common
"default" configuration, as a part of the build process.
 2020-11-13 05:44:16 +00:00
whitequark d6da4c257b build.plat: TemplatedPlatform.iter_extra_files→Platform.iter_files. 
This function was added in commit 20553b14 in the wrong place, with
the wrong name, and without tests. Fix all that.
 2020-11-10 05:30:30 +00:00