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671 commits

Author SHA1 Message Date
Alain Péteut
371dc8bebe compat.fhdl.specials: fix Tristate. 2019-04-22 08:49:08 +00:00
whitequark
93d15abcf1 compat.fhdl.specials: fix TSTriple. 2019-04-22 08:15:03 +00:00
whitequark
585514e6ed hdl.ir: rework named port handling for Instances. 
The main purpose of this rework is cleanup, to avoid specifying
the direction of input ports in an implicit, ad-hoc way using
the named ports and ports dictionaries.

While working on this I realized that output ports can be connected
to anything that is valid on LHS, so this is now supported too.
 2019-04-22 07:46:47 +00:00
whitequark
44711b7d08 hdl.ir: detect elaboratables that are created but not used. 
Requres every elaboratable to inherit from Elaboratable, but still
accepts ones that do not, with a warning.

Fixes #3.
 2019-04-21 08:52:57 +00:00
whitequark
85ae99c1b4 back.rtlil: emit nmigen.hierarchy attribute. 
Fixes #54.
 2019-04-21 07:55:08 +00:00
whitequark
360bc9b5b4 hdl.ast: improve tests for exceptional conditions. 2019-04-21 07:20:00 +00:00
whitequark
33f9bd2a1d hdl.ast: accept Signals with identical min/max bounds. 
And produce a 0-bit signal.

Fixes #58.
 2019-04-21 07:16:59 +00:00
whitequark
083016d747 back.rtlil: only expand legalized values in Array/Part context on RHS. 
Otherwise the following code fails to compile:

    index = Signal(1)
    array = Array(range(2))
    with m.If(0 == array[index]):
        m.d.sync += index.eq(0)

Fixes #51.
 2019-04-21 06:43:31 +00:00
whitequark
ce1eff5464 hdl.rec: implement Record.connect. 
Fixes #31.
 2019-04-21 06:37:08 +00:00
whitequark
f22106e5ef back.rtlil: allow record slices on LHS. 2019-04-20 08:12:29 +00:00
whitequark
611c25f909 hdl.rec: fix slicing of records. 2019-04-19 19:55:39 +00:00
whitequark
dda8f34d39 hdl.xfrm: handle classes that inherit from Record. 2019-04-18 17:06:33 +00:00
whitequark
287a0531b3 lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin. 2019-04-15 16:27:23 +00:00
whitequark
50fa2516fa hdl.ast: fix some type checks. 2019-04-10 04:33:44 +00:00
whitequark
0a2a7025a6 hdl.xfrm: allow using FragmentTransformer on any elaboratable. 
Fixes #29.
 2019-04-10 00:23:11 +00:00
whitequark
49eef77c53 hdl: remove deprecated get_fragment() and lower() methods. 2019-04-09 23:53:43 +00:00
whitequark
a74cacdc69 hdl.ast: handle a common typo, such as Signal(1, True). 2019-04-03 14:59:01 +00:00
whitequark
c9c9307a5e test_sim: add missing add_process(). 
Fixes #43.
 2019-03-28 17:50:14 +00:00
Luke Wren
23a07b955f lib.cdc: add optional reset to MultiReg, and document its use cases. 2019-03-28 05:21:48 +00:00
whitequark
a57c72d606 back.rtlil: fix off-by-one in Part legalization. 
Fixes #52.
 2019-03-28 05:12:12 +00:00
anuejn
3c95299c4e hdl.rec: separate record and signal name with __, not _. 
This makes names of signals within records less ambiguous, in case
they themselves have underscores within them.
 2019-03-25 14:26:00 +00:00
whitequark
81ee2db163 hdl.ast: fix typo. 
Fixes #49.
 2019-03-25 10:50:39 +00:00
whitequark
4027317835 lib.fifo: register GrayEncoder output before CDC. 
Without this register, static hazards in the encoder could cause
multiple encoder output bits to toggle, which would be incorrectly
sampled by the 2FF synchronizer.

Reported by @Wren6991.
 2019-03-03 18:23:51 +00:00
whitequark
e93bf4bf4b tracer: factor out get_var_name(default=). 2019-03-03 18:21:22 +00:00
whitequark
cac4b10b82 hdl.rec: remove __slots__. 
Left in by mistake.
 2019-03-03 18:21:22 +00:00
whitequark
8ee6bd80ff hdl.ir: raise a more descriptive error on non-elaboratable object. 2019-02-14 20:52:42 +00:00
whitequark
43e4833ddb back.rtlil: accept ast.Const as cell parameter. 2019-01-26 23:25:54 +00:00
whitequark
bc5a127fd2 hdl.ast: fix ValueKey for Cat. 2019-01-26 23:25:34 +00:00
whitequark
e844b0e095 compat.fhdl.module: fix typo. 2019-01-26 23:08:55 +00:00
whitequark
ce7ba70462 compat.fhdl.specials: fix __all__ list. 2019-01-26 22:59:33 +00:00
whitequark
6cd9f7db19 compat.genlib.resetsync: add shim for AsyncResetSynchronizer. 2019-01-26 18:24:36 +00:00
whitequark
2fb85a6170 compat.fifo: fix _FIFOInterface deprecation wrapper. 2019-01-26 18:23:58 +00:00
whitequark
f44ca291c1 lib.cdc: add ResetSynchronizer. 2019-01-26 18:07:59 +00:00
whitequark
e74dbc3377 back.pysim: support async reset. 2019-01-26 18:07:43 +00:00
whitequark
8686e9aa06 back.pysim: give better names to unnamed fragments and their signals. 
Was: top.#0, top.None_clk
Now: top.U0, top.U0_clk

(U for Unnamed, or similarly, an unit refdes.)
 2019-01-26 18:07:16 +00:00
whitequark
b133eb735f back.rtlil: accept any elaboratable, not just fragments. 2019-01-26 16:11:29 +00:00
whitequark
4bf80a6e33 compat: suppress deprecation warnings that are internal or during test. 2019-01-26 15:43:00 +00:00
whitequark
7890c0adc8 test.compat: reenable tests converting to Verilog. 2019-01-26 15:29:09 +00:00
whitequark
4887771e4a compat.sim: fix deprecated stdlib import. 2019-01-26 15:26:54 +00:00
whitequark
4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark
4922a73c5d test.compat: import tests from Migen as appropriate. 
test_signed and test_coding are adjusted slightly to account for
differences in comb propagation between the simulators; we might want
to revert that eventually.
 2019-01-26 01:01:03 +00:00
whitequark
f71e0fffbb hdl.ast: fix shape calculation for *. 
This was carried over from Migen, and is wrong there too.
Counterexample: 1'sd-1 * 4'sd-4 = 4'sd-4 (but should be 5'sd4).
 2019-01-26 00:56:40 +00:00
whitequark
7b25665fde back.pysim: fix behavior of initial cycle for sync processes. 
The current behavior was introduced in 65702719, which was a wrong
fix for an issue that was actually fixed in 12e04e4e. This commit
effectively reverts 65702719 and 1782b841.
 2019-01-25 20:37:56 +00:00
whitequark
1782b841b2 lib.fifo: in FIFOInterface.read(), check readable on the right cycle. 2019-01-22 07:03:46 +00:00
whitequark
eeb023a7f5 compat.genlib.fifo: adjust _FIFOInterface shim to not require fwft=. 2019-01-22 06:56:46 +00:00
whitequark
2c80f35de4 lib.fifo: fix typo in AsyncFIFO documentation. 2019-01-22 05:47:50 +00:00
whitequark
e33580cf4c lib.fifo: add AsyncFIFO and AsyncFIFOBuffered. 2019-01-21 16:02:46 +00:00
whitequark
12e04e4ee5 back.pysim: wake up processes before ever committing any values. 
Otherwise, the contract of the simulator to sync processes is not
always fulfilled.
 2019-01-21 16:00:25 +00:00
whitequark
52a9f818f1 compat.genlib.cdc: add missing import. 2019-01-20 03:03:56 +00:00
whitequark
c110fe6a9d compat.genlib.cdc: add GrayCounter and GrayDecoder shims. 2019-01-20 02:29:08 +00:00