Commit graph

825 commits

Author SHA1 Message Date
whitequark c79caead33 setup: bump pyvcd to ~=0.2.
We don't use any of the deprecated functionality, and the added
requirement of Python 3.6+ matches ours.

Having a requirement for pyvcd ~=0.1.4 was actually the cause of
the error I tried to fix in commit 6e1145e2. It had nothing to do
with Jinja2 (though it is definitely still good to have the tighter
requirement on Jinja2); the cause of the error was that pip would
install Jinja2, schedule installing markupsafe, install pyvcd 0.2.0
and then choke on the pyvcd 0.1.4 requirement, which would prevent
it from installing markupsafe &c. Why it does that is beyond me.
2020-04-02 11:23:49 +00:00
Jacob Lifshay 995f3a147b Add support for using non-compat Elaboratable instances with compat.fhdl.verilog.convert and compat.run_simulation
Fixes #344
2020-04-02 02:46:44 +00:00
whitequark 6e1145e2e7 setup: tighten version constraint on Jinja2.
I remember thinking that not constraining it properly might bite us
someday, but assumed that Jinja2 will always stay version 2. Now it
looks like Jinja2 3.0.0a1 got released, pip picks it by default, and
it's currently broken (something about markupsafe missing).

Do what needed to be done in the first place.
2020-04-02 01:35:39 +00:00
whitequark 2d1e12d00c hdl.ast: implement abs() on values. 2020-03-22 20:50:10 +00:00
WRansohoff a0d279850e
vendor.lattice_ice40: add support for SB_[LH]FOSC as default_clk.
These oscillators are only available on iCE40 UltraPlus devices.
2020-03-20 08:10:48 +00:00
Nicolas Robin 28f5eba9fb vendor: fix typo async_ff_sync 2020-03-15 11:34:52 +00:00
Stuart Olsen 7b9c8b440f
back.pysim: implement modulus operator. 2020-03-15 05:22:03 +00:00
awygle 4601dd0a69
Correctly handle resets in AsyncFIFO.
This commit improves handling of resets in AsyncFIFO in two ways:
  * First, resets no longer violate Gray counter CDC invariants.
  * Second, write domain reset now empties the entire FIFO.
2020-03-14 23:26:07 +00:00
whitequark 12c79025f3 vendor: fix a few issues in commit 2f8669ca. 2020-03-12 20:29:17 +00:00
awygle 2f8669cad6
lib.cdc: extract AsyncFFSynchronizer.
In some cases, it is necessary to synchronize a reset-like signal but
a new clock domain is not desirable. To address these cases, extract
the implementation of ResetSynchronizer into AsyncFFSynchronizer,
and replace ResetSynchronizer with a thin wrapper around it.
2020-03-08 21:37:40 +00:00
whitequark a14a5723c1 hdl.ast: fix off-by-1 in Initial.__init__(). 2020-02-19 01:28:14 +00:00
whitequark ec7aee62ea back.pysim: fix RHS codegen for Cat() and Repl(..., 0).
Fixes #325.
2020-02-19 01:21:00 +00:00
whitequark 377f2d987d back.pysim: optionally allow introspecting generated code. 2020-02-19 01:01:24 +00:00
awygle 5ae87916ec
nmigen.compat.genlib.cdc: add PulseSynchronizer. 2020-02-16 07:01:44 +00:00
awygle fcbabfeefc
nmigen.lib.cdc: port PulseSynchronizer.
Co-authored-by: Luke Wren <wren6991@gmail.com>
2020-02-16 06:51:53 +00:00
whitequark 71d9eea4a0 Travis: prune dependencies.
bitarray is not required since commit 7df70059.
2020-02-14 06:34:28 +00:00
whitequark 3fd7fe7880 Travis: test on Python 3.8. 2020-02-14 06:33:08 +00:00
whitequark 57b08dbc2c cli: update use of deprecated code. 2020-02-12 14:42:24 +00:00
whitequark 8947096eea back.pysim: accept write_vcd(vcd_file=None).
Because write_vcd() is a context manager, this is useful if the VCD
file should be sometimes not written, since it avoids awkward
conditionals with duplicated code. It's not very elegant though.

Fixes #319.
2020-02-12 14:42:06 +00:00
whitequark 38aa9fb671 setup: update project URLs. 2020-02-09 17:03:06 +00:00
whitequark 4f17cb1ac7 doc: remove outdated files and references to them. 2020-02-09 14:16:00 +00:00
whitequark 66f4510c44 README: link to IRC channel. 2020-02-08 11:00:08 +00:00
whitequark 36f498e358 README: consolidate requirements in the Installation section. 2020-02-08 10:54:01 +00:00
whitequark 3b6727152e test_build_res: fix after commit 3e2ecdf2. 2020-02-07 00:07:19 +00:00
whitequark 3e2ecdf2fb build.res,vendor: place clock constraint on port, not net, if possible.
For most toolchains, these are functionally identical, although ports
tend to work a bit better, being the common case. For Vivado, though,
it is necessary to place them on the port because its timing analyzer
considers input buffer delay.

Fixes #301.
2020-02-06 23:37:15 +00:00
whitequark 5888f29c1f xilinx_{7series,ultrascale}: run report_methodology.
This can expose important timing issues, such as #301.
2020-02-06 19:38:21 +00:00
whitequark 27b47faf16 hdl.ast: add Value.{as_signed,as_unsigned}.
Before this commit, there was no way to do so besides creating and
assigning an intermediate signal, which could not be extracted into
a helper function due to Module statefulness.

Fixes #292.
2020-02-06 18:27:55 +00:00
whitequark 9301e31b69 test_lib_fifo: define all referenced FSM states.
Broken in commit a1c58633.
2020-02-06 18:10:15 +00:00
whitequark a1c58633e6 hdl.dsl: make referencing undefined FSM states an error.
Before this commit, doing something like:

    with m.FSM():
        with m.State("FOO"):
            m.next = "bAR"
        with m.State("BAR"):
            m.next = "FOO"

would silently create an empty state `bAR` and get stuck in it until
the module is reset. This was done intentionally (in Migen, this code
would in fact miscompile), but in retrospect was clearly a bad idea;
it turns typos into bugs, while in the rare case that branching to
a completely empty state is desired, it is trivial to define one.

Fixes #315.
2020-02-06 17:47:46 +00:00
whitequark 97cc78a3db hdl.ir: type check ports.
Fixes #290.
2020-02-06 17:33:41 +00:00
whitequark 882fddfa96 back.pysim: emit toplevel inputs in VCD files as well.
Before this commit, only signals driven from fragments (in practice,
everything except toplevel inputs) would get written to a VCD file.
Not having toplevel inputs in the dump made debugging ~impossible.

After this commit, all signals the fragment refers to get written to
a VCD file. (More specifically, all signals the compiler assigns
an index to, i.e. signals the generated code reads or writes.)

Fixes #280.
2020-02-06 17:19:47 +00:00
whitequark d3775eedd7 back.pysim: make write_vcd(traces=) actually use those traces.
Reported in #280.
2020-02-06 17:07:48 +00:00
whitequark 3df429703c hdl.dsl: reject name mismatch in m.domains.<name> +=.
This would violate invariants later in the elaboration process.

Fixes #282.
2020-02-06 16:13:59 +00:00
whitequark 86b57fe6b6 hdl.dsl: type check when adding to m.domains. 2020-02-06 15:19:16 +00:00
whitequark 31cd72c0b6 hdl.mem: add synthesis attribute support.
Fixes #291.
2020-02-06 14:53:16 +00:00
whitequark f7abe368a9 hdl.mem: document Memory. 2020-02-06 13:47:13 +00:00
whitequark dfcf7938ea hdl.{ast,dsl}: allow whitespace in bit patterns.
Fixes #316.
2020-02-04 07:54:54 +00:00
whitequark a295e3599c hdl.ast: update documentation for Signal.
Fixes #288.
2020-02-01 23:15:18 +00:00
whitequark 49758a3a0c hdl.ast: prohibit shifts by signed value.
These are not desirable in a HDL, and currently elaborate to broken
RTLIL (after YosysHQ/yosys#1551); prohibit them completely, like
we already do for division and modulo.

Fixes #302.
2020-02-01 23:04:25 +00:00
whitequark cce6b8687b build.plat: align pipeline with Fragment.prepare().
Since commit 7257c20a, platform code calls create_missing_domains()
before _propagate_domains_up() (as a part of prepare() call). Since
commit a7be3b48, without a platform, create_missing_domains() is
calle after _propagate_domains_up(); because of that, it adds
the missing domain to the fragment. When platform code then calls
prepare() again, this causes an assertion failure.

The true intent behind the platform code being written this way is
that it *overrides* a part of prepare()'s mechanism. Because it was
not changed when prepare() was modified in 7257c20a, the override,
which happened to work by coincidence, stopped working. This is
now fixed by inlining the relevant parts of Fragment.prepare() into
Platform.prepare().

This is not a great solution, but given the amount of breakage this
causes (no platform-using code works), it is acceptable for now.

Fixes #307.
2020-02-01 03:26:04 +00:00
whitequark 6fd7cbad0d hdl.dsl: don't allow inheriting from Module.
`Module` is an object with a lot of complex and sometimes fragile
behavior that overrides Python attribute accessors and so on.
To prevent user designs from breaking when it is changed, it is not
supposed to be inherited from (unlike in Migen), but rather returned
from the elaborate() method. This commit makes sure it will not be
inherited from by accident (most likely by users familiar with
Migen).

Fixes #286.
2020-02-01 02:15:45 +00:00
whitequark afece15001 hdl.ast: warn on unused property statements (Assert, Assume, etc).
A property statement that is created but not added to a module is
virtually always a serious bug, since it can make formal verification
pass when it should not. Therefore, add a warning to it, similar to
UnusedElaboratable.

Doing this to all statements is possible, but many temporary ones are
created internally by nMigen, and the extensive changes required to
remove false positives are likely not worth the true positives.
We can revisit this in the future.

Fixes #303.
2020-02-01 02:03:23 +00:00
whitequark 9fb4a4f09e _unused: extract must-use logic from hdl.ir. 2020-02-01 01:35:05 +00:00
whitequark 687d3a3df7 hdl.dsl: add missing case width check for Enum values.
Fixes #305.
2020-01-31 23:14:16 +00:00
whitequark a9da9efe5b README: clarify relationship to Migen. 2020-01-31 21:10:59 +00:00
whitequark 9964fc6b57 hdl.dsl: make if m.{If,Elif,Else}(...) a syntax error.
A common typo, and hard to notice when it's silently ignored.

Fixes #284.
2020-01-31 06:37:45 +00:00
whitequark 3ac13eb8f9 back.rtlil: don't emit wires for empty signals.
Fixes #312.
2020-01-31 03:38:58 +00:00
Mike Walters b72c3fc7f6 vendor.lattice_ecp5: support internal oscillator (OSCG). 2020-01-31 03:18:36 +00:00
Jaro Habiger ec3a21939e build.dsl: allow strings to be used as connector numbers.
Fixes #311.
2020-01-31 03:11:34 +00:00
Sylvain Munaut 7792a6cd9f vendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files in extra_files 2020-01-31 02:56:19 +00:00