Commit graph

276 commits

Author SHA1 Message Date
Wanda a7a7d32099 hdl._ast: deprecate Value.implies. 2024-04-16 19:26:08 +00:00
Wanda f243cea0fb sim: implement Format.* for memories in VCD. 2024-04-15 14:54:44 +00:00
Wanda 625dac376a hdl._dsl: improve error message on m.domains.cd_foo = ....
Fixes #1331.
2024-04-15 00:32:09 +00:00
Wanda 877a1062a6 hdl._nir: add combinational cycle detection.
Fixes #704.
Fixes #1143.
2024-04-13 14:01:47 +00:00
Wanda 8bf4f77616 sim: use Format.* for VCD output, remove hdl._repr.
This also changes `decoder` a bit: when an enum is used as a decoder,
it is converted to a `Format.Enum` instead. The original enum is still
stored on the `decoder` attribute, so that it can be propagated
on `Signal.like`.
2024-04-13 10:00:16 +00:00
Wanda 122be7849c sim: raise an error when overriding a combinationally-driven signal.
Fixes #557.
2024-04-13 09:40:41 +00:00
Wanda 16f187e7fa test_build_res: fix naming, squash warnings. 2024-04-13 08:38:38 +00:00
Wanda eebffc15d6 sim: add eval_format function.
This will be used in an upcoming PR for VCD output.
2024-04-12 20:14:11 +00:00
Wanda 580706fafd hdl._nir, back.rtlil: use Format.* to emit enum attributes and wires for fields. 2024-04-11 22:02:26 +00:00
Wanda 4cb2dde25f lib.data: add .format() implementation. 2024-04-11 19:02:06 +00:00
Wanda 67f5b61bcc hdl._ast: add enum name argument to Format.Enum.
Turns out that RTLIL enum representation requires such, so add a place to store it.
2024-04-11 18:45:16 +00:00
Wanda 1fdd9bf4e9 lib.enum: add .format() implementation. 2024-04-11 14:23:26 +00:00
Wanda 3c870d6b73 hdl._ast: add Format.Enum, Format.Struct, Format.Array. 2024-04-11 10:02:54 +00:00
Wanda 6f5d009fad sim: fix LRHS evaluation.
Fixes #1269.
2024-04-11 09:42:14 +00:00
Wanda 49a8a942e8 lib.enum: rename EnumMeta to EnumType.
Fixes #1073.
2024-04-11 08:40:12 +00:00
Wanda c59447c258 hdl._ast: make Signal.like work properly with ShapeCastables.
Fixes #1285.
2024-04-11 05:03:17 +00:00
Wanda 0be2dda656 lib.data: accept data.Const in *.const(). 2024-04-11 03:20:35 +00:00
Wanda cf534489a2 build.{plat,res}: post-lib.io cleanup. 2024-04-11 03:19:38 +00:00
Wanda 7fe62f810b Implement RFC 63: Remove amaranth.lib.coding 2024-04-11 00:15:55 +00:00
Catherine 1b81a47b69 test_lib_crc: speed up tests using multiprocessing. 2024-04-10 05:08:05 +00:00
Catherine 7dd93bea57 Document RFC 62.
This includes a few minor code changes:
- Removing redundant `lib.memory.Memory.Init = hdl.MemoryData.Init`
  re-export;
- Renaming `FrozenError` to `FrozenMemory` and moving it to `.hdl`;
- Marking `ReadPort` and `WritePort` as `@final`.
2024-04-09 15:52:34 +00:00
Wanda 7936b87667 hdl._ir: add caches for Matches and PriorityMatch cells. 2024-04-06 10:25:42 +00:00
Wanda 9bd536bbf9 hdl._ir: fix SwitchValue LHS lowering. 2024-04-04 23:13:00 +00:00
Catherine d94c97981a back.rtlil: implement remaining format specifiers.
This requires a Yosys version from git. The requirement should be bumped
to a proper release before Amaranth 0.5.
2024-04-04 03:03:09 +00:00
Wanda d3c5b958d3 back.rtlil: Opportunistically trim zero and sign extension on operands.
Fixes #1148.
2024-04-04 01:55:35 +00:00
Wanda 2d59242bf7 back.rtlil: refactor to use intermediate structures.
Fixes #1100.
2024-04-04 00:58:39 +00:00
Wanda 81c35a5922 hdl._ir: remove Fragment.drivers. 2024-04-04 00:55:06 +00:00
Wanda 262e24b564 hdl._ir: Remove uses of _[lr]hs_signals and _ioports. 2024-04-03 22:01:01 +00:00
Wanda 0e6d802de4 Implement RFC 58: Core support for ValueCastable formatting. 2024-04-03 19:59:19 +00:00
Wanda f21d3d0c6a hdl._ir: add all_undef_to_ff mode. 2024-04-03 18:47:45 +00:00
Wanda 767d69c703 hdl._mem: implement MemoryData._Row from RFC 62. 2024-04-03 17:15:02 +00:00
Wanda f71bee499d sim: evaluate simulator commands in-place instead of compiling them. 2024-04-03 14:45:19 +00:00
Catherine 3c6f46717b lib.wiring: allow reset-less signals in interfaces.
This check was originally added out of abundance of caution, but since
then it was observed that reset-less-ness is purely an implementation
detail (see #1220), and furthermore it interferes with adaptation of
`FIFOInterface`` signals (where `[rw]_data` are reset-less) for RFC 61.
2024-04-03 12:01:48 +00:00
Wanda 606ebcd7a9 hdl._ast: Implement Mux in terms of SwitchValue.
Fixes #1075.
2024-04-03 11:00:58 +00:00
Wanda 466536efcf hdl._ir: raise an error when an elaboratable is duplicated in hierarchy.
Fixes #1194.
2024-04-03 10:11:07 +00:00
Wanda 2cf9bbf306 hdl._ast: add SwitchValue, reimplement ArrayProxy with it. 2024-04-03 10:01:44 +00:00
Wanda 2eb62a8b49 hdl._ast: change Switch to operate on list of cases. 2024-04-03 08:03:52 +00:00
Wanda cd6cbd71ca hdl.{_ast,_dsl}: factor out the pattern normalization logic. 2024-04-03 07:34:09 +00:00
Wanda 0e4c2de725 Implement RFC 59: Get rid of upwards propagation of clock domains 2024-04-02 17:00:42 +00:00
Wanda 09d5540430 hdl._mem: add MemoryData class.
This implements half of RFC 62. The `MemoryData._Row` class will be
implemented later, as a follow-up.
2024-04-02 14:58:23 +00:00
Wanda 1deaf70ad9 tracer: cover more CALL_* opcodes. 2024-04-02 13:30:02 +00:00
Wanda c4bbcc6f8a hdl._ast: enforce the ShapeCastable.const contract in Const(). 2024-04-02 10:24:34 +00:00
Catherine 738d8b7764 hdl: deprecate {Const,Signal}.{width,signed} accessors.
These accessors used to be necessary (in addition to `.shape()`) while
the AST nodes were mutable. However, after commit 2bf1b4da that made
AST nodes immutable, there is no technical requirement to keep them
around. Additionally:

- `len(value)` is shorter than `value.width` and works with any `value`
- `value.shape().signed` is longer than `value.signed` but works with
  any `value`
2024-03-26 22:56:17 +00:00
Wanda 0c041f2602 hdl._ir: rename Instance.named_ports to Instance.ports.
Made possible by the new port propagation code freeing up the name.
2024-03-26 20:36:12 +00:00
Thomas Watson fa2adbef84 hdl.dsl: use private names for FSM ongoing signals 2024-03-25 19:15:24 +00:00
Thomas Watson c7f719ab93 hdl.ast: allow Signals to be privately named using name=""
* Given a private name `$\d+` in RTLIL (as they are not named in the IR)

* Not automatically added to VCD files (as they are not named in the IR)

* Cannot be traced to a VCD (as they have no name to put in the file)

* Cannot be used with an unnamed top-level port (as there is no name)
2024-03-25 19:15:24 +00:00
Wanda 6ffafef794 lib.memory: raise an error on mutating already-elaborated memory. 2024-03-25 18:40:20 +00:00
Wanda efcd9a4538 hdl._ast: fix _value_repr computation.
Fixes fallout from #1165.
2024-03-25 13:53:39 +00:00
Catherine 11f7b887ad sim: write process commands to VCD file.
If delta cycles are expanded (i.e. if the `fs_per_delta` argument to
`Simulator.write_vcd` is not zero), then create a string typed variable
for each testbench in the simulation, which reflects the current
command being executed by that testbench. To make all commands visible,
insert a (visual) delta cycle after each executed command, and ensure
that there is a change/crossing point in the waveform display each time
a command is executed, even if several identical ones in a row.

If delta cycles are not expanded, the behavior is unchanged.
2024-03-24 12:21:32 +00:00
Catherine 36fb9035e4 sim: allow visualizing delta cycles in VCD dumps.
This commit adds an option `fs_per_delta=` to `Simulator.write_vcd()`.
Specifying a positive integer value for it causes the simulator to
offset value change times by that many femtoseconds for each delta
cycle after the last timeline advancement.

This option is only suitable for debugging. If the timeline is advanced
by less than the combined duration of expanded delta cycles, an error
similar to the following will be raised:

    vcd.writer.VCDPhaseError: Out of order timestamp: 62490

Typically `fs_per_delta=1` is best, since it allows thousands of delta
cycles to be expanded without risking a VCD phase error, but bigger
values can be used for an exaggerated visual effect.

Also, the VCD writer is changed to use 1 fs as the timebase instead of
1 ps. This change is largely invisible to designers, resulting only in
slightly larger VCD files due to longer timestamps.

Since the `fs_per_delta=` option is per VCD writer, it is possible to
simultaneously dump two VCDs, one with and one without delta cycle
expansion:

    with sim.write_vcd("sim.vcd"), sim.write_vcd("sim.d.vcd", fs_per_delta=1):
        sim.run()
2024-03-24 12:07:49 +00:00