Commit graph

40 commits

Author SHA1 Message Date
whitequark 2f9dab361f {,_}tools→{,_}utils
In context of nMigen, "tools" means "parts of toolchain", so it is
confusing to have a completely unrelated module also called "tools".
2019-10-13 18:53:38 +00:00
whitequark da48c05bdf _tools: extract most utility methods to a private package.
We don't want to guarantee backwards compatibility for most of them.
2019-10-12 22:40:48 +00:00
whitequark b90687c988 Rename remaining wrap methods to cast.
Following commit d72d4a55.
2019-10-11 13:28:26 +00:00
whitequark db960e7c30 Consistently use {!r}, not '{!r}' in diagnostics.
This can cause confusion:
  * If the erroneous object is None, it is printed as 'None', which
    appears as a string (and could be the result of converting None
    to a string.)
  * If the erroneous object is a string, it is printed as ''<val>'',
    which is a rather strange combination of quotes.
2019-10-11 11:47:42 +00:00
whitequark d72d4a55fd hdl.ast: Value.{wrap→cast}
Preparation for #225.
2019-10-11 10:49:34 +00:00
whitequark 1621ceb65a hdl.ast: actually implement the // operator. 2019-09-28 19:33:24 +00:00
whitequark 4b3a068b15 hdl.mem: use 1 as reset value for ReadPort.en.
This is necessary for consistency, since for transparent read ports,
we currently do not support .en at all (it is fixed at 1) due to
YosysHQ/yosys#760. Before this commit, changing port transparency
would require adding or removing an assignment to .en, which is
confusing and error-prone.

Also, most read ports are always enabled, so this behavior is also
convenient.
2019-09-20 19:51:13 +00:00
whitequark 7f6b3f93f5 back.pysim: fix simulation of Value.xor(). 2019-09-20 10:12:59 +00:00
whitequark 32310aecad hdl.ast: add Value.xor, mapping to $reduce_xor.
Fixes #147.
2019-09-13 14:29:46 +00:00
whitequark b23a9794a4 hdl.ast: add Value.{any,all}, mapping to $reduce_{or,and}.
Refs #147.
2019-09-13 13:14:52 +00:00
whitequark 72cf4ca991 back.pysim: implement sim.add_clock(if_exists=True). 2019-08-23 08:53:48 +00:00
whitequark 906385c7f8 back.pysim: don't crash when trying to drive a nonexistent domain clock. 2019-08-23 08:37:59 +00:00
whitequark 13316053e3 build.plat, hdl.ir: coordinate missing domain creation.
Platform.prepare() was completely broken after addition of local
clock domains, and only really worked before by a series of
accidents because there was a circular dependency between creation
of missing domains, fragment preparation, and insertion of pin
subfragments.

This commit untangles the dependency by adding a separate public
method Fragment.create_missing_domains(), used in build.plat.

It also makes DomainCollector consider both used and defined domains,
such that it will work on fragments before domain propagation, since
create_missing_domains() can be called by user code before prepare().

The fragment driving missing clock domain is not flattened anymore,
because flattening does not work well combined with local domains.
2019-08-19 22:52:01 +00:00
whitequark fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing.
See #57.
2019-08-03 14:54:20 +00:00
whitequark 94e13effad hdl.ast: deprecate Value.part, add Value.{bit,word}_select.
Fixes #148.
2019-08-03 13:07:06 +00:00
whitequark 94e8f479a5 hdl.mem: use read_port(domain="comb") for asynchronous read ports.
This avoids the absurdity of the combination of arguments that is
read_port(domain="sync", synchronous=True).

Fixes #116.
2019-07-01 19:56:49 +00:00
whitequark 066dd799e8 back.pysim: check for a clock being added twice.
This commit adds a best-effort error for a common mistake of adding
a clock driving the same domain twice, such as a result of
a copy-paste error.

Fixes #27.
2019-06-11 03:54:22 +00:00
whitequark c9c9307a5e test_sim: add missing add_process().
Fixes #43.
2019-03-28 17:50:14 +00:00
whitequark 4948162f33 hdl.ir: rename .get_fragment() to .elaborate().
Closes #9.
2019-01-26 02:31:12 +00:00
whitequark 7b25665fde back.pysim: fix behavior of initial cycle for sync processes.
The current behavior was introduced in 65702719, which was a wrong
fix for an issue that was actually fixed in 12e04e4e. This commit
effectively reverts 65702719 and 1782b841.
2019-01-25 20:37:56 +00:00
whitequark 12e04e4ee5 back.pysim: wake up processes before ever committing any values.
Otherwise, the contract of the simulator to sync processes is not
always fulfilled.
2019-01-21 16:00:25 +00:00
whitequark 8c96675580 hdl.ast: add Past, Stable, Rose, Fell. 2019-01-17 04:31:27 +00:00
whitequark cbf7bd6e31 back.pysim: handle non-driven, non-port signals.
Fixes #20.
2019-01-13 08:31:38 +00:00
whitequark 849c649259 back.pysim: warn if simulation is not run.
This would have prevented 3ea35b85.
2018-12-29 15:02:04 +00:00
whitequark 92a96e1644 hdl.rec: add basic record support. 2018-12-28 13:22:10 +00:00
whitequark fa2af27bb0 hdl.mem: ensure transparent read port model has correct latency. 2018-12-21 13:01:08 +00:00
whitequark 48d13e47ec back.pysim: handle out of bounds ArrayProxy indexes. 2018-12-21 12:32:08 +00:00
whitequark e58d9ec74d hdl.mem: add simulation model for memory. 2018-12-21 11:54:32 +00:00
whitequark 4199674edd back.pysim: implement *. 2018-12-18 18:02:21 +00:00
whitequark 07e9cfa939 test.sim: add tests for sync functionality and errors. 2018-12-18 17:53:50 +00:00
whitequark d4e8d3e95a back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. 2018-12-16 10:31:42 +00:00
whitequark d9579219ee test.sim: generalize assertOperator. NFC. 2018-12-15 21:08:29 +00:00
whitequark 20a04bca88 back.pysim: implement Part. 2018-12-15 20:58:06 +00:00
whitequark 54fb999c99 back.pysim: implement ArrayProxy. 2018-12-15 19:37:36 +00:00
whitequark 790eb05a92 Rename fhdl→hdl, genlib→lib. 2018-12-15 14:25:31 +00:00
whitequark b70340c0da pyback.sim: test Slice, Cat, Repl. 2018-12-15 10:09:14 +00:00
whitequark db4600d52b fhdl.ast, back.pysim: implement shifts. 2018-12-15 09:58:30 +00:00
whitequark 579feaba4e fhdl.ir: Fragment.{drive→add_driver} 2018-12-14 20:58:29 +00:00
whitequark 9307a31678 back.pysim: Simulator({gtkw_signals→traces}=). 2018-12-14 15:23:22 +00:00
whitequark 474d46ced8 back.pysim: implement most operators and add tests. 2018-12-14 14:21:22 +00:00