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  • 73244f2bd2 lib.io: style. NFC. whitequark 2019-09-12 13:51:18 +00:00
  • 9893e3c044 lib.cdc: adjust ResetSynchronizer for new CDC primitive conventions. whitequark 2019-09-12 13:48:45 +00:00
  • 8f659b6cd6 lib.cdc: adjust MultiReg for new CDC primitive conventions. whitequark 2019-09-12 13:48:24 +00:00
  • 8c30147e39 build.plat,vendor: allow clock constraints on arbitrary signals. whitequark 2019-09-11 23:35:43 +00:00
  • d1779bdb59 back: return name map from convert_fragment(). whitequark 2019-09-11 23:14:00 +00:00
  • 7342662bee hdl.ast: warn if reset value is truncated. whitequark 2019-09-10 07:25:28 +00:00
  • 27cedf4302 vendor.lattice_ecp5: pass ecppack_opts to ecppack. Darrell Harmon 2019-09-09 21:32:36 -06:00
  • 9b398b502e hdl.ast: check type of Sample(domain=...). whitequark 2019-09-08 23:55:05 +00:00
  • 3f6abc0b7a hdl.dsl: add Default(), an alias for Case() with no arguments. whitequark 2019-09-08 12:24:18 +00:00
  • eb04a2509e hdl.mem,lib,examples: use Signal.range(). whitequark 2019-09-08 12:19:13 +00:00
  • ccfbccc044 hdl.ast: add Signal.range(...), to replace Signal(min=..., max=...). whitequark 2019-09-08 12:10:31 +00:00
  • 5e9587bbbd Remove nmigen.lib from prelude. whitequark 2019-09-06 06:47:27 +00:00
  • 38831abdb4 Fix .gitignore. whitequark 2019-09-06 05:30:22 +00:00
  • 284b533995 setup: replace versioneer with setuptools_scm. whitequark 2019-09-06 05:11:41 +00:00
  • 943ce317af hdl.ast,back.rtlil: implement Cover. whitequark 2019-09-03 01:32:24 +00:00
  • 2e20622046 hdl.cd: add negedge clock domains. whitequark 2019-08-31 22:05:48 +00:00
  • c4e8ac734f _toolchain,build.plat,vendor.*: add required_tools list and checks. Emily 2019-08-31 00:27:22 +01:00
  • 4e91710933 vendor.lattice_ecp5: drive GSR synchronous to user clock by default. whitequark 2019-08-30 10:10:13 +00:00
  • a4b58cbf3a build.dsl: allow both str and int resource attributes. whitequark 2019-08-30 08:35:52 +00:00
  • 98278a044d test.tools: use _toolchain.get_tool. Emily 2019-08-28 12:52:16 +01:00
  • b14f5572d8 _toolchain: new module, for injecting dependencies in e.g. Nix. whitequark 2019-08-28 11:32:18 +00:00
  • 2168ff512b back.verilog: bump Yosys version requirement to 0.9. whitequark 2019-08-26 09:35:37 +00:00
  • b4b5d9e2ef vendor.lattice_ecp5: revert default toolchain to Trellis. whitequark 2019-08-25 08:07:00 +00:00
  • 72cf4ca991 back.pysim: implement sim.add_clock(if_exists=True). whitequark 2019-08-23 08:53:48 +00:00
  • 906385c7f8 back.pysim: don't crash when trying to drive a nonexistent domain clock. whitequark 2019-08-23 08:37:59 +00:00
  • 9350620f89 build.run: add BuildPlan.digest(), useful for caching. whitequark 2019-08-23 01:10:51 +00:00
  • 7fc1058ed2 vendor.lattice_ecp5: add Diamond support. whitequark 2019-08-20 12:27:19 +00:00
  • c77274c1ad vendor: eliminate unnecessary LUT instantiation. whitequark 2019-08-22 20:54:42 +00:00
  • b0ef53e095 examples/basic/uart: document divisor parameter. Reto Kramer 2019-08-22 12:28:40 -07:00
  • 47bad3d20e back.rtlil: print real parameters with maximum precision. whitequark 2019-08-22 04:42:30 +00:00
  • aefde85031 back.rtlil: add support for real (float) parameters on Instances. Darrell Harmon 2019-08-21 22:13:05 -06:00
  • 6737ef79f9 vendor.xilinx_series7: use STARTUPE2, not STARTUPE3. Darrell Harmon 2019-08-21 16:25:55 -06:00
  • 5889e62668 vendor.lattice_ice40: remove --placer heap default option. whitequark 2019-08-21 21:32:12 +00:00
  • 531040d2fd vendor: style. NFC. whitequark 2019-08-21 21:31:19 +00:00
  • 25b280dba1 build.plat: remove TemplatedPlatform.unix_interpreter. whitequark 2019-08-21 21:02:05 +00:00
  • 1fc63a62c0 back.pysim: allow coroutines as processes. whitequark 2019-08-21 03:28:48 +00:00
  • c934fc66e9 test.test_examples: Convert pathlib-specific class to string. William D. Jones 2019-08-04 21:52:23 -04:00
  • 5ad409e897 back.verilog: parse output of yosys -V. whitequark 2019-08-19 23:28:33 +00:00
  • 7ca29a5748 Fix nmigen.__version__ to work on git-archive artifacts. whitequark 2019-08-19 23:14:41 +00:00
  • 13316053e3 build.plat, hdl.ir: coordinate missing domain creation. whitequark 2019-08-19 22:32:50 +00:00
  • 77012fc143 vendor.lattice_ice40: use a local clock domain in create_missing_domain(). whitequark 2019-08-19 21:46:44 +00:00
  • a069d975b2 lib.cdc: use a local clock domain in ResetSynchronizer. whitequark 2019-08-19 20:47:40 +00:00
  • 71ee64c403 README: fix typos. whitequark 2019-08-19 21:44:23 +00:00
  • 003ba3b45f hdl.cd: implement local clock domains. whitequark 2019-08-19 20:46:46 +00:00
  • 9bdadbff09 back.pysim: index domains by identity, not by name. whitequark 2019-08-19 21:29:53 +00:00
  • 69d36dc139 hdl.xfrm: lower resets in DomainLowerer as well. whitequark 2019-08-19 21:32:48 +00:00
  • 404f99f022 hdl.xfrm: consider fragment's own domains in DomainLowerer. whitequark 2019-08-19 21:06:54 +00:00
  • 32bfbb11cb formal→asserts whitequark 2019-08-19 20:23:24 +00:00
  • 2770db6de8 tracer: fix typo. whitequark 2019-08-19 20:20:18 +00:00
  • ada1d6a603 build.plat: do not prepare fragments twice. whitequark 2019-08-19 19:29:47 +00:00
  • a2241fcfdb back.{rtlil,verilog}: split convert_fragment() off convert(). whitequark 2019-08-19 19:27:02 +00:00
  • 8e048c5a7c build.dsl: add conn argument to Connector. Robin Heinemann 2019-08-18 21:56:25 +02:00
  • 84f2c3df2b compat.fhdl.decorators: avoid using deprecated NativeCEInserter. whitequark 2019-08-18 16:27:11 +00:00
  • d44ea4e9fe hdl.xfrm: make deprecated CEInserter more well-behaved. whitequark 2019-08-18 16:26:45 +00:00
  • ed7e07c6c1 hdl.ast: implement Initial. whitequark 2019-08-15 02:53:07 +00:00
  • 40abaef858 hdl.xfrm: sample cache should be per-fragment. whitequark 2019-08-15 02:42:14 +00:00
  • fa0fa056ba hdl.xfrm: CEInserter→EnableInserter. whitequark 2019-08-12 13:37:18 +00:00
  • 9d2cbbabb8 hdl.ast: hash-cons ValueKey. whitequark 2019-08-08 10:56:23 +00:00
  • 4ee82c9584 tracer: use sys._getframe directly. whitequark 2019-08-08 10:23:35 +00:00
  • e6b1e3de1a compat.fhdl.decorators: port from oMigen. whitequark 2019-08-08 08:09:28 +00:00
  • 5c626e33bf compat.fhdl.module: fix finalization of transformed compat submodules. whitequark 2019-08-08 07:45:34 +00:00
  • 1b379a513c vendor.lattice_ice40: add iCE5LP2K support. whitequark 2019-08-07 09:25:20 +00:00
  • cfbc678508 vendor.lattice_ice40: add iCE40UP3K support. whitequark 2019-08-07 09:06:27 +00:00
  • 9c35e44e4a vendor.lattice_ice40: add iCE5LP1K support. whitequark 2019-08-07 09:00:41 +00:00
  • 434b686d5e vendor.xilinx_{spartan_3_6,7series}: reconsider default reset logic. whitequark 2019-08-04 23:27:47 +00:00
  • 3d7214cb70 vendor.xilinx_spartan_3_6: reconsider bitgen defaults. whitequark 2019-08-04 23:23:06 +00:00
  • 27063a3bd3 vendor.xilinx_spartan_3_6: set bitgen defaults to -g Binary:Yes -g Compress. whitequark 2019-08-04 14:16:02 +00:00
  • 65da905c15 vendor.xilinx_spartan_3_6: always use -w for map/par/bitgen. whitequark 2019-08-04 14:12:02 +00:00
  • 15e8dfe532 vendor.xilinx_spartan_3_6: do not use retiming by default. whitequark 2019-08-04 13:48:33 +00:00
  • 6b025df12c vendor.xilinx_spartan_3_6: force use of bash on UNIX. whitequark 2019-08-04 13:19:50 +00:00
  • 5eb4e2ee51 build.plat: allow selecting a specific UNIX shell interpreter. whitequark 2019-08-04 13:18:29 +00:00
  • 34a97b2751 vendor.lattice_ice40: avoid routing conflicts with SDR/DDR input pins. whitequark 2019-08-04 00:30:50 +00:00
  • 2e6627c4af back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS. whitequark 2019-08-03 23:57:50 +00:00
  • d0ac8bf789 back.rtlil: actually match shape of left hand side. whitequark 2019-08-03 23:43:57 +00:00
  • 999a2f612a vendor.lattice_ice40: add missing signal indexing. whitequark 2019-08-03 22:59:33 +00:00
  • 8dd54ac544 build.run: use keyword-only arguments where appropriate. whitequark 2019-08-03 22:52:58 +00:00
  • 0fe05188e8 compat.fhdl.specials: track changes in build.plat. whitequark 2019-08-03 22:52:34 +00:00
  • 99d205494a hdl.dsl: reword m.If(~True) warning to be more clear. whitequark 2019-08-03 18:52:24 +00:00
  • 8854ca03ae build.plat,vendor: automatically create sync domain from default_clk. whitequark 2019-08-03 18:36:58 +00:00
  • e0b54b417e hdl.ir: allow adding more than one domain in missing domain callback. whitequark 2019-08-03 18:19:40 +00:00
  • 9c28b61d9f hdl.ir: don't expose as ports missing domains added via elaboratables. whitequark 2019-08-03 16:39:21 +00:00
  • 21f2f8c46e build.plat: add default_rst, to be used with default_clk. whitequark 2019-08-03 16:28:03 +00:00
  • 4dbb5352ad build.plat: add default_clk{,_constraint,_frequency}. whitequark 2019-08-03 16:18:46 +00:00
  • cea92e9531 hdl.ir: allow returning elaboratables from missing domain callback. whitequark 2019-08-03 15:44:02 +00:00
  • fc846532c7 hdl.ir: raise DomainError if a domain is used but not defined. whitequark 2019-08-03 15:31:00 +00:00
  • fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing. whitequark 2019-08-03 14:54:20 +00:00
  • ace2b5ff0a hdl.dsl: warn on suspicious statements like m.If(~True):. whitequark 2019-08-03 14:00:29 +00:00
  • ab5426ce74 Improve test added in 29fee01f to not leak warnings. whitequark 2019-08-03 13:44:44 +00:00
  • ee03eab52f back.rtlil: fix sim-synth mismatch with assigns following switches. whitequark 2019-08-03 13:27:47 +00:00
  • 0a603b3844 hdl.ast: fix typo. whitequark 2019-08-03 13:21:09 +00:00
  • 94e13effad hdl.ast: deprecate Value.part, add Value.{bit,word}_select. whitequark 2019-08-03 13:05:41 +00:00
  • bcdc280a87 hdl.ast, back.rtlil: add source locations to anonymous wires. whitequark 2019-08-03 12:44:52 +00:00
  • 29fee01f86 hdl.ir: warn if .elaborate() returns None. whitequark 2019-08-03 12:30:39 +00:00
  • 995e4adb8c hdl.xfrm: handle mem.{Read,Write}Port in CEInserter. whitequark 2019-07-31 05:19:24 +00:00
  • 5fd8a796ae vendor: don't emit duplicate iobuf submodule names. N. Engelhardt 2019-07-21 15:49:21 +08:00
  • 698b005182 hdl.dsl: add getters to m.submodules. N. Engelhardt 2019-07-19 20:39:47 +08:00
  • 81e59832fb lib.fifo: fix typo. Alain Péteut 2019-07-15 00:28:06 +02:00
  • ff343d5cf0 Pin: Add extra hierarchy level for name derivation Staf Verhaegen 2019-07-14 21:15:09 +02:00
  • b963449b41 build.run: Ensure batch script returns proper error code. William D. Jones 2019-07-14 13:28:19 -04:00
  • ee15538cf0 back.pysim: correctly add gtkwave traces for signals with decoders. whitequark 2019-07-12 12:17:18 +00:00