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  • 12e8fe484d build.dsl: fix precondition check in Pins. whitequark 2019-06-06 20:40:49 +0000
  • f26e612899 vendor.xilinx_7series: implement. Jean-François Nguyen 2019-06-06 13:53:17 +0200
  • b45c5119f5 build.res: allow querying frequency of a previously constrained clock. whitequark 2019-06-05 12:51:53 +0000
  • c9879c795b build.{dsl,res,plat}: apply clock constraints to signals, not resources. whitequark 2019-06-05 08:48:36 +0000
  • ab3f103e5a build.dsl: replace extras= with Attrs(). whitequark 2019-06-05 07:02:08 +0000
  • c52cd72d3e Typos and style fixes. NFC. whitequark 2019-06-05 02:48:41 +0000
  • 452c4b380b vendor.lattice_ice40: normalize device names. whitequark 2019-06-04 16:09:08 +0000
  • 4379a5d6fe hdl.ir: rephrase elaboratable warning to not look like an error. whitequark 2019-06-04 13:11:15 +0000
  • 537d91851d compat.fhdl.module: silence "unused elaboratable" warnings. whitequark 2019-06-04 13:09:36 +0000
  • 38917e4523 compat.fhdl.specials: fix platform lowering for TSTriple again. whitequark 2019-06-04 13:03:56 +0000
  • 79a3710255 compat.fhdl.specials: fix platform lowering. whitequark 2019-06-04 12:26:09 +0000
  • 0cbb743df9 compat.fhdl.module: implement some TODO'd deprecation warnings. whitequark 2019-06-04 12:00:02 +0000
  • 3adce21ce3 build.run: fix product extraction to work on Windows. whitequark 2019-06-04 11:40:56 +0000
  • 63c4123f6e build.plat: hide executed commands in quiet builds on Windows. whitequark 2019-06-04 11:34:18 +0000
  • 1d3e9c8331 build.plat: allow (easily) overriding with an empty string on Windows. whitequark 2019-06-04 11:33:51 +0000
  • 39ca0e6fa6 compat.fhdl.module: CompatModule should be elaboratable. whitequark 2019-06-04 11:10:46 +0000
  • 4310254103 build.res: use ConstraintError iff a constraint invariant is violated. whitequark 2019-06-04 10:23:27 +0000
  • 51c03ca391 hdl.xfrm: handle empty lhs in LHSGroup{Analyzer,Filter}. whitequark 2019-06-04 10:19:54 +0000
  • 1b54eb80da vendor.board: split off into nmigen-boards package. whitequark 2019-06-04 09:47:04 +0000
  • 316ba10207 build.run: simplify using build products locally, e.g. for programming. whitequark 2019-06-04 09:13:24 +0000
  • 2763b403f1 build.res: simplify emission of port constraints on individual bits. whitequark 2019-06-04 08:37:52 +0000
  • 9f643ce005 Clean up imports. whitequark 2019-06-04 08:18:50 +0000
  • 3194b5c90b build.run: extract from build.plat. whitequark 2019-06-04 07:53:34 +0000
  • c89c2ce941 vendor.board.tinyfpga_bx: clk16 pin does not have a global buffer. whitequark 2019-06-04 06:43:10 +0000
  • 45d1dc1d54 vendor.board.tinyfpga_bx: fix typo. whitequark 2019-06-04 06:20:01 +0000
  • 6426b90e4a vendor.conn.pmod: implement. whitequark 2019-06-03 16:47:41 +0000
  • 3d04122d55 examples: reorganize into examples/basic and examples/board. whitequark 2019-06-03 16:16:44 +0000
  • 0fa45b5e14 vendor.board: extract package. whitequark 2019-06-03 16:14:59 +0000
  • 2ca0834d41 vendor.tinyfpga_bx: add connectors. whitequark 2019-06-03 15:38:49 +0000
  • 7c5461d210 vendor.icestick: add connectors. whitequark 2019-06-03 15:03:43 +0000
  • f351e2bd1e vendor.ice40_hx1k_blink_evn: add (some) connectors. whitequark 2019-06-03 15:03:34 +0000
  • ed64880cc4 build.{plat,res}: add support for connectors. whitequark 2019-06-03 15:02:15 +0000
  • a013eb1f59 build.dsl: add support for connectors. whitequark 2019-06-03 13:03:49 +0000
  • 4c443a7ef5 compat.fhdl.specials: TSTriple is not an elaboratable. whitequark 2019-06-03 09:39:38 +0000
  • 639e64c388 vendor.fpga.lattice_ice40: implement differential output buffers. whitequark 2019-06-03 09:23:11 +0000
  • 41adcc3f97 vendor.fpga.lattice_ice40: implement differential input buffers. whitequark 2019-06-03 08:38:12 +0000
  • 3116d4add2 vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO via extras. whitequark 2019-06-03 07:54:28 +0000
  • 185abb492d vendor.fpga.lattice_ice40: implement SDR and DDR I/O buffers. whitequark 2019-06-03 07:43:02 +0000
  • b42043f764 lib.io: add i_clk and o_clk to pin layout with xdr>=1. whitequark 2019-06-03 05:56:18 +0000
  • a1940c5528 hdl.rec: unbreak hasattr(rec, ...). whitequark 2019-06-03 07:16:09 +0000
  • 6fae06aea9 build.{dsl,plat,res}: allow dir="oe". whitequark 2019-06-03 04:39:05 +0000
  • 1eee7cd76f lib.io: allow dir="oe". whitequark 2019-06-03 04:28:53 +0000
  • 9ba2efd86b build.{res,plat}: use xdr=0 as default, not xdr=1. whitequark 2019-06-03 03:32:30 +0000
  • cd6488c782 build.res: allow requesting raw ports, with dir="-". whitequark 2019-06-03 03:17:20 +0000
  • c30617fc05 lib.io: allow Pin(xdr=0), representing a combinatorial I/O buffer. whitequark 2019-06-03 03:29:27 +0000
  • 3327deae92 vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files. whitequark 2019-06-03 03:01:56 +0000
  • f417725b10 build.res: if not specified, request resource #0. whitequark 2019-06-03 02:54:17 +0000
  • dc17d06fe9 vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras. whitequark 2019-06-03 02:48:55 +0000
  • c6a0761b3a hdl.ir: accept LHS signals like slices as Instance io ports. whitequark 2019-06-03 02:39:14 +0000
  • b8a61edc2f hdl.dsl: allow adding submodules with computed name, like with domains. whitequark 2019-06-03 02:22:55 +0000
  • b64a31255c hdl.ir: accept expanded (kind, name, value) tuples in Instance. whitequark 2019-06-03 02:12:01 +0000
  • fb01854372 build.{res,plat}: propagate extras to pin fragment factories. whitequark 2019-06-03 01:58:43 +0000
  • 268fe6330e build.res: simplify. NFC. whitequark 2019-06-03 01:28:34 +0000
  • 98497b2075 build.dsl: require a dict for extras instead of a stringly array. whitequark 2019-06-02 23:36:21 +0000
  • e4ebe03115 vendor.fpga.lattice_ice40: use .bin suffix for bitstream tempfiles. whitequark 2019-06-02 04:12:50 +0000
  • 37152c733e vendor.tinyfpga_{b→bx} whitequark 2019-06-02 04:11:06 +0000
  • bff08c5016 vendor.tinyfpga_b: fix IO_STANDARD. whitequark 2019-06-02 04:04:07 +0000
  • 358b98e5de vendor.tinyfpga_b: implement. Simon Kirkby 2019-06-02 09:20:09 +0800
  • 39fad9a955 vendor.icestick: fix typo. whitequark 2019-06-02 01:13:03 +0000
  • 8306c9cd63 Travis: update install script. whitequark 2019-06-01 17:09:41 +0000
  • ba0fcddb2c vendor.ice40_hx1k_blink_evn: implement. whitequark 2019-06-01 16:47:47 +0000
  • eab372383a vendor.icestick: implement. whitequark 2019-06-01 16:47:20 +0000
  • 321d245e95 vendor.fpga.lattice_ice40: implement. whitequark 2019-06-01 16:46:50 +0000
  • b1eab9fb3b build.plat: implement. whitequark 2019-06-01 16:43:27 +0000
  • 53ddff9f33 build.res: always return a Pin record. whitequark 2019-06-01 16:41:30 +0000
  • 8c1b5a26b3 build.res: accept a list of clocks in ConstraintManager constructor. whitequark 2019-06-01 15:41:41 +0000
  • f17375a60b back.rtlil: allow specifying platform for convert(). whitequark 2019-05-26 17:10:56 +0000
  • 578dba263f Add versioneer. whitequark 2019-05-26 11:20:13 +0000
  • b0ba960296 hdl.ir: silence unused elaboratable warning on interpreter crash. whitequark 2019-05-26 10:42:52 +0000
  • d393c5ec64 build.res: add ConstraintManager. Jean-François Nguyen 2019-04-26 14:37:08 +0200
  • 3a9fe31133 build.dsl: make Pins and DiffPairs iterable. whitequark 2019-05-25 22:37:32 +0000
  • 48145cee02 build.dsl: improve repr of Pins() and DiffPairs(). whitequark 2019-05-25 22:23:03 +0000
  • 2b7dc37ffe hdl.rec: allow providing fields during construction. whitequark 2019-05-25 21:57:07 +0000
  • 3392708e2b Consider Instances a part of containing fragment for use-def purposes. whitequark 2019-05-25 20:09:26 +0000
  • 699fe5a675 Add import so that Tristate.elaborate builds Chris Osterwood 2019-05-20 07:39:21 -0700
  • c337246fc5 hdl.ir: when adding sync domain to a design, also add it to ports. whitequark 2019-05-15 06:44:50 +0000
  • 39bc59c924 hdl.ir: during port propagation, defs should take priority over uses. whitequark 2019-05-13 15:34:13 +0000
  • 921f506e69 back.rtlil: assign undriven signals to their reset value. whitequark 2019-05-13 07:56:11 +0000
  • 744e33f42d hdl: make all public Value classes other than Record final. whitequark 2019-05-12 05:36:35 +0000
  • 958cb18b88 hdl.ir: only pull explicitly specified ports to toplevel, if any. whitequark 2019-05-12 05:21:23 +0000
  • 6a77122c2e lib.io: add a name argument to the Pin constructor. Jean-François Nguyen 2019-04-24 23:58:01 +0200
  • a982fbe377 build.dsl: style. NFC. whitequark 2019-04-24 15:02:30 +0000
  • dd5bd1c88d build: add DSL for defining platform resources. Jean-François Nguyen 2019-04-18 20:11:15 +0200
  • 97af266645 back.verilog: allow stripping the src attribute, for cleaner output. whitequark 2019-04-22 14:08:01 +0000
  • c8e92c0612 compat.fhdl.specials: fix Tristate, TSTriple. Alain Péteut 2019-04-22 11:57:12 +0200
  • 371dc8bebe compat.fhdl.specials: fix Tristate. Alain Péteut 2019-04-22 10:37:06 +0200
  • 93d15abcf1 compat.fhdl.specials: fix TSTriple. whitequark 2019-04-22 08:15:03 +0000
  • 585514e6ed hdl.ir: rework named port handling for Instances. whitequark 2019-04-22 07:46:47 +0000
  • aed2062101 Remove examples/tbuf.py. whitequark 2019-04-21 08:53:37 +0000
  • 44711b7d08 hdl.ir: detect elaboratables that are created but not used. whitequark 2019-04-21 08:52:57 +0000
  • 85ae99c1b4 back.rtlil: emit nmigen.hierarchy attribute. whitequark 2019-04-21 07:55:08 +0000
  • 360bc9b5b4 hdl.ast: improve tests for exceptional conditions. whitequark 2019-04-21 07:20:00 +0000
  • 33f9bd2a1d hdl.ast: accept Signals with identical min/max bounds. whitequark 2019-04-21 07:16:59 +0000
  • 083016d747 back.rtlil: only expand legalized values in Array/Part context on RHS. whitequark 2019-04-21 06:41:35 +0000
  • ce1eff5464 hdl.rec: implement Record.connect. whitequark 2019-04-21 06:37:08 +0000
  • f22106e5ef back.rtlil: allow record slices on LHS. whitequark 2019-04-20 08:12:29 +0000
  • 611c25f909 hdl.rec: fix slicing of records. whitequark 2019-04-19 19:55:39 +0000
  • dda8f34d39 hdl.xfrm: handle classes that inherit from Record. whitequark 2019-04-18 17:06:33 +0000
  • 287a0531b3 lib.io: rework TSTriple/Tristate interface to use pin_layout/Pin. whitequark 2019-04-15 16:27:23 +0000
  • 50fa2516fa hdl.ast: fix some type checks. whitequark 2019-04-10 04:33:44 +0000