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  • 73ed870309 compat.genlib.coding: fix import. Jean-François Nguyen 2018-12-26 15:29:48 +0100
  • 528747703d lib.coding: port from Migen. whitequark 2018-12-26 13:19:34 +0000
  • fe8cb55204 lib.cdc: add tests for MultiReg. whitequark 2018-12-26 12:58:30 +0000
  • 35a44f017f hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too. whitequark 2018-12-26 12:42:43 +0000
  • 934546e633 hdl.dsl: provide generated values for FSMs. whitequark 2018-12-26 12:39:05 +0000
  • 040811c2e5 hdl.ir: add an API for retrieving generated values, like FSM signal. whitequark 2018-12-26 12:35:27 +0000
  • 597d778cf6 examples: add an FSM usage example (UART receiver). whitequark 2018-12-26 10:10:27 +0000
  • 72039b6072 hdl.dsl: add signal decoder to FSM state signal. whitequark 2018-12-26 09:45:12 +0000
  • 54e3195dcb hdl.dsl: implement FSM. whitequark 2018-12-26 08:55:04 +0000
  • b4fbef65ca back.rtlil: clarify $verilog_initial_trigger behavior. NFC. whitequark 2018-12-26 06:45:57 +0000
  • 010ddb96b5 back.rtlil: unbreak d47c1f8a. whitequark 2018-12-24 19:11:07 +0000
  • f05bd2a137 hdl.mem: allow omitting memory simulation logic. whitequark 2018-12-24 09:31:51 +0000
  • d47c1f8a8a back.rtlil: use one $meminit cell, not one per word. whitequark 2018-12-24 09:30:47 +0000
  • 98f554aa08 hdl.xfrm, back.rtlil: implement and use LHSGroupFilter. whitequark 2018-12-24 02:17:28 +0000
  • 1c7c75a254 hdl.xfrm: implement SwitchCleaner, for pruning empty switches. whitequark 2018-12-24 02:02:59 +0000
  • fc0fb9d89f back.rtlil: always output negative values as two's complement. whitequark 2018-12-24 01:38:32 +0000
  • 5702767263 back.rtlil: emit dummy logic to work around Verilog deficiencies. whitequark 2018-12-23 10:14:05 +0000
  • 9faa1d3742 back.rtlil: do not translate empty fragments. whitequark 2018-12-23 09:20:02 +0000
  • 45a474788c back.rtlil: only translate switch tests once. whitequark 2018-12-23 07:17:33 +0000
  • 4e49772f67 cli: generate: guess file type from extension. whitequark 2018-12-23 07:13:17 +0000
  • 2b6ddbb713 back.rtlil: fix swapped operands in mux codegen. whitequark 2018-12-23 06:47:38 +0000
  • cf79738744 cli: new module, for basic design generaton/simulation. whitequark 2018-12-22 23:56:02 +0000
  • 621dddebfd hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer. whitequark 2018-12-22 22:19:14 +0000
  • 3448953f61 compat.genlib.fsm: fix naming for non-Signal LHS. whitequark 2018-12-22 22:00:58 +0000
  • 68dae9f50e hdl.ir: flatten hierarchy based on memory accesses, too. whitequark 2018-12-22 21:43:46 +0000
  • fd89d2fc9d hdl.ir: factor out _merge_subfragment. NFC. whitequark 2018-12-22 19:04:35 +0000
  • 59c7540aeb back.rtlil: split processes as finely as possible. whitequark 2018-12-22 10:03:16 +0000
  • d29929912f back.rtlil: remove useless condition. NFC. whitequark 2018-12-22 07:24:15 +0000
  • ae0cb48fbb hdl.xfrm: implement LHSGroupAnalyzer. whitequark 2018-12-22 06:50:32 +0000
  • 98a9744be4 hdl.xfrm: Abstract*Transformer→*Visitor whitequark 2018-12-22 06:03:38 +0000
  • 37b81309d3 back.rtlil: always initialize the entire memory. whitequark 2018-12-22 05:27:42 +0000
  • 99b778158d compat: use nicer names for next_value/next_value_ce signals. whitequark 2018-12-22 02:05:49 +0000
  • 8730895d8c hdl.mem: allow changing init value after creating memory. whitequark 2018-12-22 01:09:03 +0000
  • 6ee80408bb back.verilog: do not rename internal signals. whitequark 2018-12-22 00:53:40 +0000
  • 5361b4c22b compat: fix confusing naming for memory port address signal. whitequark 2018-12-22 00:53:05 +0000
  • f6772759c8 hdl.ir: fix port propagation between siblings, in the other direction. whitequark 2018-12-22 00:31:31 +0000
  • 0df543b204 compat: do not finalize native submodules twice. whitequark 2018-12-22 00:02:31 +0000
  • a4183eba69 hdl.mem: use more informative signal naming for ports. whitequark 2018-12-21 23:55:02 +0000
  • 913339c04a hdl.ir: fix port propagation between siblings. whitequark 2018-12-21 23:53:18 +0000
  • 00ef7a78d3 compat: provide verilog.convert shim. whitequark 2018-12-21 13:53:06 +0000
  • fc7da1be2d hdl.ir: do not flatten instances or collect ports from their statements. whitequark 2018-12-21 13:52:18 +0000
  • 568d3c5b7d compat: provide Memory shim. whitequark 2018-12-21 13:15:52 +0000
  • fa2af27bb0 hdl.mem: ensure transparent read port model has correct latency. whitequark 2018-12-21 13:01:08 +0000
  • 48d13e47ec back.pysim: handle out of bounds ArrayProxy indexes. whitequark 2018-12-21 12:32:08 +0000
  • 7ae7683fed back.pysim: give numeric names to unnamed subfragments in VCD. whitequark 2018-12-21 12:29:33 +0000
  • af7db882c0 hdl.mem: use different naming for array signals. whitequark 2018-12-21 12:26:49 +0000
  • e58d9ec74d hdl.mem: add simulation model for memory. whitequark 2018-12-21 11:00:42 +0000
  • a40e2cac4b back.pysim: fix an issue with too few funclet slots. whitequark 2018-12-21 10:25:28 +0000
  • c49211c76a hdl.mem: add tests for all error conditions. whitequark 2018-12-21 06:07:16 +0000
  • a061bfaa6c hdl.mem: tie rdport.en high for asynchronous or transparent ports. whitequark 2018-12-21 04:22:16 +0000
  • 8d58cbf230 back.rtlil: more consistent prefixing for subfragment port wires. whitequark 2018-12-21 04:21:11 +0000
  • b0bd7bfaca hdl.ir: correctly handle named output and inout ports. whitequark 2018-12-21 04:03:03 +0000
  • 2b4a8510ca back.rtlil: implement memories. whitequark 2018-12-21 01:55:59 +0000
  • 6d9a6b5d84 hdl.mem: implement memories. whitequark 2018-12-21 01:53:32 +0000
  • 6672ab2e3f back.rtlil: explicitly pad constants with zeroes. whitequark 2018-12-21 01:51:18 +0000
  • 221f108fbe back.rtlil: fix translation of Cat. whitequark 2018-12-21 01:48:02 +0000
  • f7fec804ec ir: allow non-Signals in Instance ports. whitequark 2018-12-20 23:38:01 +0000
  • 8cc900c4ef setup: update pyvcd dependency, for var_type="string". whitequark 2018-12-19 17:17:25 +0000
  • 0f2c7e7161 compat: import genlib.record from Migen. whitequark 2018-12-18 20:04:22 +0000
  • a90748303c compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices. whitequark 2018-12-18 20:02:32 +0000
  • dbbcc49a71 hdl.ast: Cat.{operands→parts} whitequark 2018-12-18 19:15:44 +0000
  • 4199674edd back.pysim: implement *. whitequark 2018-12-18 18:02:21 +0000
  • 07e9cfa939 test.sim: add tests for sync functionality and errors. whitequark 2018-12-18 17:53:50 +0000
  • 7fa82a70be back.pysim: eliminate most dictionary lookups. whitequark 2018-12-18 15:28:27 +0000
  • 7341d0d7ef hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim. whitequark 2018-12-18 15:06:02 +0000
  • c5f169988b back.pysim: use arrays instead of dicts for signal values. whitequark 2018-12-18 05:19:12 +0000
  • 39605ef551 back.pysim: naming. NFC. whitequark 2018-12-18 04:46:36 +0000
  • 65702719e8 back.pysim: fix an off-by-1 in add_sync_process(). whitequark 2018-12-18 04:43:04 +0000
  • 34b81d0b87 back.pysim: trigger processes waiting on Tick() exactly at clock edge. whitequark 2018-12-18 04:37:39 +0000
  • d6e98fd934 back.pysim: continue running simulator processes until they suspend. whitequark 2018-12-18 03:05:16 +0000
  • 51a92bc870 Travis: cache Yosys installation explicitly. whitequark 2018-12-17 23:46:46 +0000
  • c7f9386eab fhdl.ir: add black-box fragments, fragment parameters, and Instance. whitequark 2018-12-17 22:55:30 +0000
  • de6c12af77 Travis: build and cache Yosys. whitequark 2018-12-17 15:51:55 +0000
  • 8d1639a5a8 hdl, back: add and use SignalSet/SignalDict. whitequark 2018-12-17 17:21:12 +0000
  • 8c4de99c0d hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC. whitequark 2018-12-17 17:13:08 +0000
  • f1e390cbc9 back.rtlil: update for Yosys master. whitequark 2018-12-17 15:50:43 +0000
  • 850674637a back.rtlil: implement Array. whitequark 2018-12-17 01:15:23 +0000
  • 87cd045ac3 back.rtlil: implement Part. whitequark 2018-12-17 01:05:08 +0000
  • f968678937 back.rtlil: handle reset_less domains. whitequark 2018-12-16 23:52:47 +0000
  • 015998eba9 hdl.dsl: add clock domain support. whitequark 2018-12-16 23:51:24 +0000
  • b2f828387a hdl.dsl: cleanup. NFC. whitequark 2018-12-16 23:44:00 +0000
  • 91b7561a00 back.rtlil: extract _StatementCompiler. NFC. whitequark 2018-12-16 22:26:58 +0000
  • b9a0af8bde back.rtlil: simplify. NFC. whitequark 2018-12-16 21:00:00 +0000
  • 635094350f back.rtlil: properly escape strings in attributes. whitequark 2018-12-16 20:27:15 +0000
  • 41d69c3ad7 README: mention Yosys requirement. whitequark 2018-12-16 18:09:01 +0000
  • 33f32a25f5 back.rtlil: prepare for Yosys sigspec slicing improvements. whitequark 2018-12-16 18:03:14 +0000
  • db5fd1e4c4 compat.fhdl.structure: only convert to bool in If/Elif if necessary. whitequark 2018-12-16 17:41:42 +0000
  • 9bce35098f back.rtlil: avoid illegal slices. whitequark 2018-12-16 17:41:11 +0000
  • e86104d3a6 back.rtlil: use slicing to match shape when reducing width. whitequark 2018-12-16 16:20:45 +0000
  • 2833b36c73 back.rtlil: don't emit a slice if all bits are used. whitequark 2018-12-16 16:05:38 +0000
  • 9794e732e2 back.rtlil: reorganize value compiler into LHS/RHS. whitequark 2018-12-16 13:30:20 +0000
  • ed39748889 back.rtlil: fix naming. NFC. whitequark 2018-12-16 11:26:31 +0000
  • 2be76fda3c hdl.xfrm: separate AST traversal from AST identity mapping. whitequark 2018-12-16 11:24:23 +0000
  • 286a8009c8 compat.fhdl: reexport Array. whitequark 2018-12-16 10:38:25 +0000
  • d4e8d3e95a back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. whitequark 2018-12-16 10:31:42 +0000
  • d9579219ee test.sim: generalize assertOperator. NFC. whitequark 2018-12-15 21:08:29 +0000
  • bdb8db2826 back.pysim: add (stub) LHSValueCompiler. whitequark 2018-12-15 21:01:38 +0000
  • 20a04bca88 back.pysim: implement Part. whitequark 2018-12-15 20:58:06 +0000
  • 1adf58f561 examples: rename clkdiv/ctrl to ctr/ctr_ce. whitequark 2018-12-15 20:42:52 +0000
  • 6c601fecfa doc: update COMPAT_SUMMARY. whitequark 2018-12-15 20:40:51 +0000