usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity
1636 commits 1 branch 0 tags 3.8 MiB
Commit graph

1636 commits

This branch
This branch
All branches
Author SHA1 Message Date
Catherine 3103841eee docs/stdlib/data: use :py: role. NFC 2024-04-10 01:30:10 +00:00
Catherine 1a962cc405 docs: remove all generated WaveDrom diagrams. 2024-04-10 01:30:10 +00:00
Wanda 4f6b0f23c2 vendor.{_gowin,_lattice_*}: fix DDR buffer naming. 2024-04-10 00:15:42 +00:00
Wanda 545aee7733 vendor._lattice_ecp5: fix input domain in FFBuffer. 2024-04-09 23:42:24 +00:00
Wanda 16e80a7dcf vendor._lattice_machxo_2_3l: implement lib.io buffer primitives. 2024-04-09 22:41:23 +00:00
Sage Walker 514ff0bcbc build.run: fix execute_local_docker() not exiting docker container on SIGINT 2024-04-09 22:07:36 +00:00
Wanda cd083aac14 vendor._gowin: implement lib.io buffer primitives. 2024-04-09 19:46:19 +00:00
Catherine d28d15761d vendor: LatticeICE40Platform→SiliconBluePlatform. 
Devices originally designed by SiliconBlue have one set of primitives,
and devices originally designed by AT&T, Alcatel-Lucent, or Lattice
have a different set of primitives. This is the first step in merging
the non-SiliconBlue Lattice platforms into one.
 2024-04-09 19:31:51 +00:00
Wanda 0597ac08ff vendor._lattice_ecp5: implement lib.io buffer primitives. 2024-04-09 19:22:00 +00:00
Wanda 1b9290188b vendor._altera: implement lib.io buffer primitives. 2024-04-09 18:24:36 +00:00
Catherine 7dd93bea57 Document RFC 62. 
This includes a few minor code changes:
- Removing redundant `lib.memory.Memory.Init = hdl.MemoryData.Init`
  re-export;
- Renaming `FrozenError` to `FrozenMemory` and moving it to `.hdl`;
- Marking `ReadPort` and `WritePort` as `@final`.
 2024-04-09 15:52:34 +00:00
Wanda 38ad35757b build.res: give a more specific error for add_clock_constraint(ClockSignal). 
Fixes #542.
 2024-04-07 09:54:47 +00:00
Catherine 6fb5f3f120 docs/memory: use wavedrom directive for diagrams. 2024-04-07 08:03:44 +00:00
Wanda 7936b87667 hdl._ir: add caches for Matches and PriorityMatch cells. 2024-04-06 10:25:42 +00:00
Catherine df589a54e0 _toolchain.yosys: fix amaranth-yosys version extractor. 2024-04-06 08:01:49 +00:00
Wanda 6857daff54 vendor._lattice_ice40: implement lib.io buffer primitives. 2024-04-05 04:07:29 +00:00
Wanda 4e3550db43 build.plat: use lib.io.*Buffer in default platform. 2024-04-04 23:57:48 +00:00
Wanda 9bd536bbf9 hdl._ir: fix SwitchValue LHS lowering. 2024-04-04 23:13:00 +00:00
Wanda 572d546e07 back.rtlil: fix use of deprecated Signal.width. 2024-04-04 22:35:42 +00:00
Catherine d94c97981a back.rtlil: implement remaining format specifiers. 
This requires a Yosys version from git. The requirement should be bumped
to a proper release before Amaranth 0.5.
 2024-04-04 03:03:09 +00:00
Wanda d3c5b958d3 back.rtlil: Opportunistically trim zero and sign extension on operands. 
Fixes #1148.
 2024-04-04 01:55:35 +00:00
Wanda 2d59242bf7 back.rtlil: refactor to use intermediate structures. 
Fixes #1100.
 2024-04-04 00:58:39 +00:00
Wanda 81c35a5922 hdl._ir: remove Fragment.drivers. 2024-04-04 00:55:06 +00:00
Wanda 262e24b564 hdl._ir: Remove uses of _[lr]hs_signals and _ioports. 2024-04-03 22:01:01 +00:00
Wanda 0e6d802de4 Implement RFC 58: Core support for ValueCastable formatting. 2024-04-03 19:59:19 +00:00
Wanda f21d3d0c6a hdl._ir: add all_undef_to_ff mode. 2024-04-03 18:47:45 +00:00
Wanda 767d69c703 hdl._mem: implement MemoryData._Row from RFC 62. 2024-04-03 17:15:02 +00:00
Wanda 93ef89626e docs: add links to more docs versions. 2024-04-03 16:15:25 +00:00
Wanda f71bee499d sim: evaluate simulator commands in-place instead of compiling them. 2024-04-03 14:45:19 +00:00
Catherine 967dabc2fe docs/{guide,reference}: clarify semantics of a.any() vs a.bool(). 2024-04-03 13:29:19 +00:00
Catherine 3c6f46717b lib.wiring: allow reset-less signals in interfaces. 
This check was originally added out of abundance of caution, but since
then it was observed that reset-less-ness is purely an implementation
detail (see #1220), and furthermore it interferes with adaptation of
`FIFOInterface`` signals (where `[rw]_data` are reset-less) for RFC 61.
 2024-04-03 12:01:48 +00:00
Wanda 606ebcd7a9 hdl._ast: Implement Mux in terms of SwitchValue. 
Fixes #1075.
 2024-04-03 11:00:58 +00:00
Wanda 466536efcf hdl._ir: raise an error when an elaboratable is duplicated in hierarchy. 
Fixes #1194.
 2024-04-03 10:11:07 +00:00
Wanda 2cf9bbf306 hdl._ast: add SwitchValue, reimplement ArrayProxy with it. 2024-04-03 10:01:44 +00:00
Wanda 2eb62a8b49 hdl._ast: change Switch to operate on list of cases. 2024-04-03 08:03:52 +00:00
Wanda cd6cbd71ca hdl.{_ast,_dsl}: factor out the pattern normalization logic. 2024-04-03 07:34:09 +00:00
Wanda 0e4c2de725 Implement RFC 59: Get rid of upwards propagation of clock domains 2024-04-02 17:00:42 +00:00
Wanda 09d5540430 hdl._mem: add MemoryData class. 
This implements half of RFC 62. The `MemoryData._Row` class will be
implemented later, as a follow-up.
 2024-04-02 14:58:23 +00:00
Wanda 1deaf70ad9 tracer: cover more CALL_* opcodes. 2024-04-02 13:30:02 +00:00
Wanda c4bbcc6f8a hdl._ast: enforce the ShapeCastable.const contract in Const(). 2024-04-02 10:24:34 +00:00
Wanda 5577f4e703 hdl._ir: Fix Array lowering with 0-width index. 2024-03-28 02:24:25 +00:00
Wanda 1d5de80347 lib.data: fix wrong class name on Struct and Union. 2024-03-27 15:00:09 +00:00
Catherine f261071f7c docs/guide: clarify section on IOBufferInstance. 
There is no reason to assign names to `IOBufferInstance` submodules
because it's ignored anyways.
 2024-03-26 23:21:29 +00:00
Catherine 738d8b7764 hdl: deprecate {Const,Signal}.{width,signed} accessors. 
These accessors used to be necessary (in addition to `.shape()`) while
the AST nodes were mutable. However, after commit 2bf1b4da that made
AST nodes immutable, there is no technical requirement to keep them
around. Additionally:

- `len(value)` is shorter than `value.width` and works with any `value`
- `value.shape().signed` is longer than `value.signed` but works with
  any `value`
 2024-03-26 22:56:17 +00:00
Wanda 0c041f2602 hdl._ir: rename Instance.named_ports to Instance.ports. 
Made possible by the new port propagation code freeing up the name.
 2024-03-26 20:36:12 +00:00
Thomas Watson fa2adbef84 hdl.dsl: use private names for FSM ongoing signals 2024-03-25 19:15:24 +00:00
Thomas Watson c7f719ab93 hdl.ast: allow Signals to be privately named using name="" 
* Given a private name `$\d+` in RTLIL (as they are not named in the IR)

* Not automatically added to VCD files (as they are not named in the IR)

* Cannot be traced to a VCD (as they have no name to put in the file)

* Cannot be used with an unnamed top-level port (as there is no name)
 2024-03-25 19:15:24 +00:00
Wanda 6ffafef794 lib.memory: raise an error on mutating already-elaborated memory. 2024-03-25 18:40:20 +00:00
Catherine 3d5c36a606 docs/reference: finish Value section. 2024-03-25 16:03:55 +00:00
Wanda cd51e02de2 lib.wiring: remove stray references to signature freezing. 2024-03-25 14:15:53 +00:00