usb-tools/amaranth
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity
792 commits 1 branch 0 tags 3.8 MiB
Commit graph

37 commits

Author SHA1 Message Date
whitequark 86b57fe6b6 hdl.dsl: type check when adding to m.domains. 2020-02-06 15:19:16 +00:00
whitequark dfcf7938ea hdl.{ast,dsl}: allow whitespace in bit patterns. 
Fixes #316.
 2020-02-04 07:54:54 +00:00
whitequark 6fd7cbad0d hdl.dsl: don't allow inheriting from Module. 
`Module` is an object with a lot of complex and sometimes fragile
behavior that overrides Python attribute accessors and so on.
To prevent user designs from breaking when it is changed, it is not
supposed to be inherited from (unlike in Migen), but rather returned
from the elaborate() method. This commit makes sure it will not be
inherited from by accident (most likely by users familiar with
Migen).

Fixes #286.
 2020-02-01 02:15:45 +00:00
whitequark 687d3a3df7 hdl.dsl: add missing case width check for Enum values. 
Fixes #305.
 2020-01-31 23:14:16 +00:00
whitequark 9964fc6b57 hdl.dsl: make if m.{If,Elif,Else}(...) a syntax error. 
A common typo, and hard to notice when it's silently ignored.

Fixes #284.
 2020-01-31 06:37:45 +00:00
whitequark 75d0fcd639 test: use #nmigen: magic comment instead of monkey patch. 
Also, fix missing and incorrect src_loc_at arguments where
appropriate so the testsuite passes without warnings.
 2019-10-26 06:37:08 +00:00
whitequark 2f9dab361f {,_}tools→{,_}utils 
In context of nMigen, "tools" means "parts of toolchain", so it is
confusing to have a completely unrelated module also called "tools".
 2019-10-13 18:53:38 +00:00
whitequark 706bfaf5e1 hdl.ast: deprecate Signal.{range,enum}. 
Although constructor methods can improve clarity, there are many
contexts in which it is useful to use range() as a shape: notably
Layout, but also Const and AnyConst/AnyValue. Instead of duplicating
these constructor methods everywhere (which is not even easily
possible for Layout), use casting to Shape, introduced in 6aabdc0a.

Fixes #225.
 2019-10-11 13:07:42 +00:00
whitequark db960e7c30 Consistently use {!r}, not '{!r}' in diagnostics. 
This can cause confusion:
  * If the erroneous object is None, it is printed as 'None', which
    appears as a string (and could be the result of converting None
    to a string.)
  * If the erroneous object is a string, it is printed as ''<val>'',
    which is a rather strange combination of quotes.
 2019-10-11 11:47:42 +00:00
whitequark 450d7efdf2 hdl.dsl: add a diagnostic for m.d.submodules += .... 2019-09-28 17:50:24 +00:00
whitequark 4777a7b3a2 hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns. 
Fixes #207.
 2019-09-16 19:22:12 +00:00
whitequark f292a1977c hdl.dsl: improve error messages for Case(). 2019-09-14 20:58:19 +00:00
whitequark 3f6abc0b7a hdl.dsl: add Default(), an alias for Case() with no arguments. 
Fixes #197.
 2019-09-08 12:24:18 +00:00
whitequark 943ce317af hdl.ast,back.rtlil: implement Cover. 
Fixes #194.
 2019-09-03 01:32:24 +00:00
whitequark 99d205494a hdl.dsl: reword m.If(~True) warning to be more clear. 
Before this commit, it only suggested one thing (silencing it) and
that's wrong almost all of the time, so suggest the right thing
instead.
 2019-08-03 18:52:24 +00:00
whitequark ace2b5ff0a hdl.dsl: warn on suspicious statements like m.If(~True):. 
This pattern usually produces an extremely hard to notice bug that
will usually break a design when it is triggered, but will also be
hidden unless the pathological value of a boolean switch is used.

Fixes #159.
 2019-08-03 14:00:29 +00:00
N. Engelhardt 698b005182 hdl.dsl: add getters to m.submodules. 2019-07-19 12:39:47 +00:00
whitequark a7fbff94d8 hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain. 
Fixes #125.
 2019-07-08 10:26:49 +00:00
whitequark da1f58b7ae hdl.dsl: further clarify error message for incorrect nesting. 
Fixes #133.
 2019-07-07 01:03:59 +00:00
whitequark cb8be4a1b0 hdl.dsl: clarify error message for incorrect nesting. 
Refs #133.
 2019-07-07 00:59:57 +00:00
whitequark 3388b5b085 hdl.dsl: gracefully handle FSM with no states. 2019-07-07 00:59:34 +00:00
whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
 2019-06-28 04:37:08 +00:00
whitequark e5e23644a4 hdl.{ast,dst}: directly represent RTLIL default case. 
This makes RTLIL mildly nicer:

 casez ({ \$5 , \$3 , \$1  })
   3'bzz1:
       \$next\o  = \$7 ;
   3'bz1z:
       \$next\o  = \$9 ;
   3'b1zz:
       \$next\o  = \$11 ;
-  3'bz:
+  default:
       { \$next\co , \$next\o  } = \$13 ;
 endcase
 2019-06-25 22:01:14 +00:00
whitequark b8a61edc2f hdl.dsl: allow adding submodules with computed name, like with domains. 2019-06-03 02:22:55 +00:00
whitequark 4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark 8c96675580 hdl.ast: add Past, Stable, Rose, Fell. 2019-01-17 04:31:27 +00:00
whitequark 011bf2258e hdl: make ClockSignal and ResetSignal usable on LHS. 
Fixes #8.
 2019-01-14 15:38:16 +00:00
whitequark 664b4bcb3a hdl.dsl: cases wider than switch test value are unreachable. 
In 3083c1d6 they were erroneously fixed via truncation.
 2019-01-13 08:51:49 +00:00
whitequark 3083c1d6dd hdl.dsl: accept (but warn on) cases wider than switch test value. 
Fixes #13.
 2019-01-13 08:46:28 +00:00
William D. Jones 2412650f56 hdl.dsl: Support Assert and Assume where an Assign can occur. 2019-01-02 11:17:39 +00:00
whitequark 470d66934f hdl.dsl: add support for fsm.ongoing(). 2018-12-27 16:19:01 +00:00
whitequark 35a44f017f hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too. 2018-12-26 12:42:43 +00:00
whitequark 934546e633 hdl.dsl: provide generated values for FSMs. 2018-12-26 12:39:05 +00:00
whitequark 54e3195dcb hdl.dsl: implement FSM. 2018-12-26 08:55:04 +00:00
whitequark 8d1639a5a8 hdl, back: add and use SignalSet/SignalDict. 2018-12-17 17:21:29 +00:00
whitequark 015998eba9 hdl.dsl: add clock domain support. 2018-12-16 23:51:24 +00:00
whitequark c6e7a93717 hdl: appropriately rename tests. NFC. 2018-12-15 16:13:53 +00:00
Renamed from nmigen/test/test_fhdl_dsl.py (Browse further)