This was an especially insidious bug because the minus character is
valid in case values but has a completely different meaning (wildcard
rather than sign).
Fixes#559.
The OpenOCD scripts for EOS-S3 are roughly equivalent to SVF files
for a more traditional FPGA, which we also produce, for some common
"default" configuration, as a part of the build process.
Commit abbebf8e used __getattr__ to proxy Value methods called on
Record. However, that did not proxy operators like __add__ because
Python looks up the special operator methods directly on the class
and does not run __getattr__ if they are missing.
Instead of using __getattr__, explicitly enumerate and wrap every
Value method that should be proxied. This also ensures backwards
compatibility if more methods are added to Value later.
Fixes#533.
These only matter in simulation and after conversion to Verilog.
During synthesis they cause Yosys to produce warnings:
Warning: Wire $verilog_initial_trigger has an unprocessed 'init' attribute.
The Zynq driver in the FPGA Manager framework on Linux expects bitstreams that
are byte swapped with respect to what the Vivado command
`write_bitstream -bin_file` produces. Thus, use the `write_cfgmem` command with
appropriate options to generate the bitstream (.bin file).
Fixes#519.
* Add invert= argument to DiffPairs() constructor, like in Pins().
* Make PinsN() and DiffPairsN() pass invert= to the corresponding
construtor instead of mutating.
I.e. on this code, which is currently not only wrongly accepted but
also results in completely unexpected RTL:
with m.If(...):
with m.Elif(...):
...
Fixes#500.
Before this commit, `_check_feature(valid_xdrs=0)` would mean that
XDR buffers are not supported. Only `_check_feature(valid_xdrs=())`
was intended to be an indicator of that.
Yosys offers no stability guarantees for individual `proc_*` passes,
though so far it worked out fine. This commit changes the Verilog
backend to use `proc -nomux` instead, which is guaranteed to have
backwards-compatible behavior.
Fixes#479.
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.
This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.
This commit completely rearranges simulation code.
1. sim._base defines internal simulation interfaces. The clarity of
these internal interfaces is important because simulation
engines mix and match components to provide a consistent API
regardless of the chosen engine.
2. sim.core defines the external simulation interface: the commands
and the simulator facade. The facade provides a single entry
point and, when possible, validates or lowers user input.
It also imports built-in simulation engines by their symbolic
name, avoiding eager imports of pyvcd or ctypes.
3. sim.xxxsim (currently, only sim.pysim) defines the simulator
implementation: time and state management, process scheduling,
and waveform dumping.
The new simulator structure has none of the downsides of the old one.
See #324.
